Items Tagged with 'DesignCon Paper'

Traditional data-center physical layer architectures have undergone a significant transition due to the growth of east-west traffic within the data center for AI/ML cluster applications. This data growth has driven enormous demand for throughput in both chip-to-chip and chip-to-module channels. In this paper, which was awarded Best Paper Award at DesignCon 2025, the authors explore various physical layer design improvements through simulation and modeling tools.

This paper covers a study previously presented at DesignCon 2025 in which a novel SI-PI layout optimization methodology and via routing pattern were developed to address challenges and enable UCIe-xA64 connections to achieve 36 Gbps in Organic Interposer packaging. This summary provides an overview of the challenges, innovations, and methodologies presented in the study, offering solutions for high-speed multi-die system integration.

This paper, previously presented at DesignCon 2025, introduces a comprehensive framework for achieving 12.8 Gbps HBM3/4-to-SoC integration using innovative interposer technologies. This summary covers the key methodologies, findings, and implications of the study, focusing on practical solutions to SI-PI challenges in HBM interfaces.

Awarded the Best Paper Award at DesignCon 2024, this paper demonstrates that, for correlated data with PDN impedances in the sub-mΩ level, the impedance extracted from same-location top-bottom measurement can be significantly different from same-side adjacent via pair measurement, even if the physical separation is in the order of a mm

This paper, awarded the Best Paper Award at DesignCon 2024, explores what is meant by bandwidth during the standardization process, the implications of test and verification attached to certain bandwidth requirements, as well as differences between acquisition range, band limited filters, and s-parameters for time domain processing. 

In order to study what is needed and what has been adopted for the next Ethernet speed node of 200 Gbps per lane, this DesignCon 2024 paper, a recipient of the Best Paper Award, investigates different FEC schemes such as end-end, concatenated, and segmented FECs, examining how these different FEC schemes affect signal integrity and performance in different end applications. 

This DesignCon 2024 paper, a Best Paper Award winner, introduces a new process utilizing heuristics to determine laminate anisotropy based on Dk/Df construction tables provided by laminate suppliers.

This DesignCon paper showcases high-speed design and testing schemes for LPO systems from a system perspective while also presenting the testing results, data, and product architecture of a linear direct-drive switch in conjunction with an LPO module system.

This paper comprehensively addresses the numerous challenges presented when designing a power distribution network for a scalable 2000 Amp power supply and provides a complete process for designing, simulating, and validating a 2000 Amp core power rail. 

This paper addresses the challenge of how to simulate the power integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation.