Traditional data-center physical layer architectures have undergone a significant transition due to the growth of east-west traffic within the data center for AI/ML cluster applications. This data growth has driven enormous demand for throughput in both chip-to-chip and chip-to-module channels. In the DesignCon 2025 paper, “Beyond 200G: Brick Walls of 400G Links per Lane," the authors explore various physical layer design improvements through simulation and modeling tools.
Connector Design Changes Required
Front-panel connectors such as QSFP and OSFP, in their different versions, may no longer have adequate performance because of their inherent wipe tail created at the point of contact between the connector spring and the PCB microstrip finger. This wipe can create resonances as low as 60 GHz, well below the Nyquist frequency required of 424 Gbps with- PAM4 encoding.
Several times in the past, copper cable solutions at increased bit rates were projected to be unfeasible, however, cable manufacturers were able to deliver acceptable solutions with a compromise of physical reach. This paper examines potential candidates to replace traditional connectors, including embedded electrical-to-optical converters using co-packaged assembly substrates.
For copper solutions, various design improvements are explored including new copper cable assemblies, better SERDES signal processing, and better control of the characteristic impedance of the channel. This paper also reviews interconnect transition design as a means to enhance channel performance.
Challenges to Reach 400 Gbps Links
From this work, it can be concluded that traditional solutions using the typical ASIC-PCB-connector-module topologies will not be able to support 424 Gbps channels using traditional signal integrity metrics for channel bandwidth. Therefore, new solutions are required to implement channels operating at 424 Gbps PAM4 including consideration of structures, encodings, etc. A move to higher modulation schemes, such as PAM6, PAM8, and PAM16, is also considered.
Alternative Architectures
Basic emitter relationships limit PCB interconnect physical size to sub-wavelength features above 80 GHz. In addition, the achievable insertion loss performance in planar interconnect is bounded from the finite conductivity of copper. So, a clearer picture is emerging for the need of alternate silicon-to-silicon channel topologies and even cabinet-level packaging architectures.
Figure 1. Co-packaged copper topology, showing the co-packaged chip-to-chip (C2C) silicon/twinax cable configuration and measured insertion loss. (Data for a Samtec Si-Fly® HD 224 Gbps PAM4, co-packaged chip system.)Figure 1 presents a new topology, a co-packaged connector, where the PCB serves more as a tray providing power, out of band and infrastructure signaling rather than being part of the physical channel for blade level network links. (The PCB baseboard could still be used for nearest neighbor node to node meshing with short C2C topologies.)
With the co-packed silicon/twinax cable topology shown in Figure 1, excessive channel loss per unit reach and large scale leaky interconnect is immediately mitigated through co-packaging the twinax cable and silicon on a common substrate. Through these efforts, 100 GHz linear insertion loss can be achieved for blade level links, allowing successful operation of a PAM6 implementation of a 424 Gbps bit rate link.
Simply scaling traditional switched-fabric star topologies using cabled chip-to-module (C2M) links to the front panel will become cable reach limited and may drive a transition to optics and the associated system penalty tradeoffs.
One way to achieve engineering design space in this instance involves leveraging orthogonal board packaging concepts at the cabinet level. In orthogonal board packaging architectures, the interface plane becomes one board (the switch) connecting to many boards (the blade stack) providing a simple geometry advantage in achieving shorter direct physical distance between nodes. Figure 2 shows these short C2C over PCB, medium C2C with co-packed twinax, and C2M links co-existing with host CPUs, accelerate nodes, and switches.
Figure 2. Orthogonal board system concept showing support for various network topologies.Conclusions
Using detailed examples, this paper explores loss due to radiation and reflection of resonance features in PCB-based topologies as potential “brick walls” to achieving more than 80 GHz of signaling frequency. Lack of physical scaling of traditional PCB based implementations to match SERDES capability and data rate demand suggests that front panel pluggable interfaces based on edge cards and baseboard routing may not be adequate to implement a 424 Gbps bit rate link. New topologies and higher order modulation techniques have been presented as potential alternatives. Much work is ongoing to find adequate solutions both in hardware and software to enable communication channels operating beyond 212 Gbps PAM4.
The paper referenced here was a Best Paper Award Winner at DesignCon 2025. To read the full paper, download the PDF.
