Universal Chiplet Interconnect Express (UCIe) is revolutionizing multi-die system integration, enabling high-performance solutions for data centers and AI-driven semiconductors. With market demands pushing for 36 Gbps die-to-die connections, the industry faces significant Signal Integrity (SI) and Power Integrity (PI) challenges, particularly in Organic Interposer technology. While Silicon Interposer technology handles UCIe-36 Gbps requirements with relative ease due to its smaller vias and trace dimensions, Organic Interposers present formidable obstacles, including larger via enclosures, trace width limitations, and high crosstalk.
In this recent research, a novel SI-PI layout optimization methodology and via routing pattern were developed to address these challenges and enable UCIe-xA64 connections to achieve 36 Gbps in Organic Interposer packaging. This summary provides an overview of the challenges, innovations, and methodologies presented in the study, offering solutions for high-speed multi-die system integration.
The Need for Innovation in UCIe Integration
UCIe-x64 (UCIe-xA64) die-to-die connections, with a 45µm diagonal micro bump pitch, face significant challenges in Organic Interposer packaging. The constraints of larger vias, stringent trace widths, and spacing requirements create high crosstalk and limit signal fanout within the 388.8µm shoreline width, preventing compliance with 36 Gbps requirements.
While Silicon Interposer technology handles these requirements seamlessly, Organic Interposer remains a critical choice for larger System-on-Chip (SoC) designs due to its cost-effectiveness and reliability. To meet the demands of high-speed data transmission in Organic Interposer, innovative methodologies and designs are essential.
Key Innovations and Contributions
The study presents a hybrid layout optimization methodology and a groundbreaking via routing pattern designed specifically for Organic Interposers. Key contributions include:
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Hybrid SI-PI Methodology:
By combining 2D and 3D Electromagnetic (EM) extraction tools, accuracy and simulation speed are balanced, enabling efficient layout optimization without compromising precision. -
Voltage Transfer Function (VTF) Characterization:
Using VTF metrics, including Insertion Loss (IL) and Crosstalk, and introducing the VTF Insertion Loss to Crosstalk Ratio (VTF ICR), UCIe channels are evaluated and optimized to meet performance requirements. -
Novel Via Fanout and Routing Pattern:
The innovative pattern strategically places Via fanout regions between 45µm diagonal pitch micro bumps, facilitating Ground-Signal-Ground (GSG) routing within the micro bump pin field. This design minimizes crosstalk and ensures successful signal fanout at 36 Gbps. -
Optimized Layout Parameters:
Eleven layout cases were evaluated, with Case 4 demonstrating optimal performance with an ICR of 34.7 dB. This configuration uses 2 µm signal trace width, 8.6 µm ground trace width, and 2 µm spacing, effectively balancing signal integrity and layout feasibility.
Overcoming Organic Interposer Challenges
The study highlights the unique challenges of implementing GSG routing in Organic Interposers. The larger via enclosures and stringent spacing requirements complicate signal fanout within the micro bump field. To address these issues, the novel via fanout pattern creates wide signal passages and alternates layer assignments, reducing congestion and improving performance.
Despite these innovations, traditional 3D EM tools remain time-consuming for layout optimization. The hybrid methodology integrates 2D tools for quick parameter sweeps and 3D tools for final model validation, ensuring efficient and accurate design iterations.
System-level EYE simulations further validate the effectiveness of the optimized layouts, demonstrating compliance with UCIe-36 Gbps requirements while maintaining reliability and scalability.
Conclusion
The UCIe-xA64 die-to-die connection at 36 Gbps represents the forefront of multi-die system integration challenges. While Silicon Interposer technology offers a straightforward solution, the complexities of Organic Interposer demand innovative approaches.
The hybrid SI-PI methodology, combined with the novel via fanout and routing pattern, provides a robust framework for achieving 36 Gbps in Organic Interposer packaging. By addressing crosstalk, optimizing layout parameters, and leveraging advanced characterization techniques like VTF ICR, the study meets the stringent requirements of high-speed UCIe connections.
This work underscores the importance of continuous innovation in advanced packaging technologies. As multi-die systems grow in complexity and demand, solutions like those presented in this study will drive the next generation of high-performance semiconductor applications.
The paper referenced here was originally published as a DesignCon 2025 paper. To read the full paper, download the PDF.
