We live in an increasingly interconnected world, one in which mobile communications provide a significant element of this interconnectivity. This increasing demand for high speed, low latency networks supporting mobile connectivity is leading the definition of 5th generation mobile networks. These next generation networks are driven not only by changing user demands such as video and cloud applications, but also by the Internet of Things (IoT) and Industrial Internet of Things (IIoT). Both of which introduce machine to machine communication, and in the case of IIOT require reliable networks and low latency response times for critical applications. 5G networks challenge network operators and equipment OEMs as different frequency bands across geographic locations and regulatory environments will present the need to support multiple air interfaces requiring adaptable solutions.

Current 4G network infrastructure presents several issues which limit its ability to scale and support next generation networks. Typically, these consist of antenna arrays and connected radio heads, mounted on now familiar cell towers. Depending upon the architecture, these towers may provide for an integrated radio head and antenna or a distributed approach. Increasingly to provide better system performance and reduce loses in the coaxial cabling required for the distributed solution, an integrated approach is used.

However, even this integrated approach to the antenna array does not provide the capacity to implement 5G networks being unable to support the number of connected devices at the data rates required. Simply put, the tower cannot support the number of antennas required to support 5G infrastructure.

Fig 1

Figure 1. Evolution from 4G tower to MIMO

To address this Massive Multiple Input Multiple Output (Massive MIMO) architectures are being considered to provide 5G network infrastructure. These consist of multiple antenna systems potentially of up to 1024 antenna. Massive MIMO therefore provides the ability to implement fine grain beam forming, enabling spatial multiplexing. This means that each of the beams can support the full bandwidth, as it is focuses the emitted energy within the beam, it offers increased RF power efficiency. Massive MIMO solutions also enable a message to be broken up and transmitted simultaneously over different paths using multiple antenna.

This change in antenna architecture allows for ultra-densification as antenna tiles can be deployed on buildings, structures and other parts of the surrounding infrastructure moving away from the cell tower. This is especially true if millimetre wavelength communications are used to provide the back-haul capabilities in place of a wired back haul.  This change in antenna deployment also brings with it constraints on the radio unit connected to the antenna; constraining not only energy efficiency but also form factor and scalability to scale from small to large scale antenna deployments without radical architectural changes.

It is not just, however, the demands of the 5G infrastructure which present challenges, network operators also bring constraints in the frequency planning. The frequency plan will vary from operator to operator depending upon their licencing and geographic location, but the solution must be configurable to support these use cases.

Embedded System Level Challenges

5G radio units therefore face several challenges in their design to ensure scalability and power efficiency. To support small antenna deployments the core of the radio architecture must be tightly integrated to be able to connect with a small number of antennas at a high data rates. The traditional approach to this challenge would be the combination of a multi giga sample ADCs and DACs with a System on Chip. This approach provides the ability to perform the embedded system design e.g. virtualisation, CloudRAN etc. within the SoC processor cores. While the programmable logic within the SoC is used to implement the ADC/DAC interfaces and signal processing pipeline.

Such an approach however, requires significant board space to implement the SoC with its supporting peripherals, and the analog front end containing the DAC and ADC. To ensure RF performance is not compromised, separation between devices must be maintained along with following stringent and time consuming layout rules. The more channels required in the solution the more complex addressing the routing signal and power integrity becomes. Solving this increases the form factor of the final solution. To address the increased operating bandwidths required for direct conversion, many data convertors implement interfaces which use JESD204B these interfaces bring with them multiple issues in the design. JESD204B interconnects take FPGA resources and increase the power dissipation of the solution.

This distributed solution therefore presents an increased power dissipation, typical high performance ADCs may require 2.25 W while DACs would be in the order of 1.75 W, in addition to the power dissipation of the JESD204B transceivers. This not only increases the board space required, but also increases the power dissipation of the overall solution. While the additional steps required in the design of the solution increase both the time taken for development, increasing the non-recurring engineering and development costs along with manufacturing and bill of material costs.

To solve the challenge presented by the network operator licensing and geographical restrictions, the use of direct RF sampling reduces the analog front end components required. Direct sampling is enabled by using ADC and DAC devices with a high sampling frequency and a wide analog input bandwidth, allowing the RF signal to be directly sampled. This removes the need for analog front end, which down convert the signal into the ADC sampling window. These analog front ends are also not programmable or easily adaptable to support licensing or geographic restrictions which requires OEM to use different frequency bands.  Designing these analog front ends requires specialised skills in the design and careful consideration of the component selection, placement and routing. The designer must also consider component drift with aging and temperature. Direct sampling removes the need for many of these components allowing the processing to be performed within the digital domain. However, it does come with a trade-off, in that higher sampling discrete ADC and DAC required to directly sample the RF signal have a higher power dissipation.

Fig 2

Figure 2. Direct vs IF conversion

The solution to these design challenges is to leverage even tighter integration, advanced CMOS technology to reduce power dissipation and allow analog to leverage Moore’s law. This is achieved by integrating the ADC and DAC devices within the SoC. Such integration provides for a more optimal solution, targeting massive MIMO applications.

RFSoC concept

The RFSoC concept does just that integrating the multi giga sample ADCs and DACs within the same silicon as the SoC, which contains the processing system and programmable logic. This offers a much tighter integrated solution providing the potential for both reduced footprint and power dissipation, while providing a direct sampling RF solution for 5G applications. Integration of ADC and DAC is not on its own sufficient to address the challenges. To fully address these, the RFSoC must also contain mixers, numerically controlled oscillators, be able to correct gain and phase and support either real or In-phase and Quadrature formatting to realize a fully integrated RFSoC. To further aid system performance, the RFSoC concept also includes optimised processing applications such as Digital Down Conversion and Digital Up Conversion close to the ADC and DAC.

The tightly integrated format of the RFSoC concept enables the device to offer a reduced board area when compared to a similar discrete solution. A typically DAC or ADC may require up to 15mm by 15mm of board space, an application which requires 8 convertors of either type would therefore requires 1800 mm2 of board space. A similar RFSoC solution typically could be packaged in a 30mm by 30mm packaging requiring only 900 mm2 of board space a significant reduction.

Providing this tightly integrated solution not only reduces the required board area but also reduces the overall power dissipation. As power scales with the sampling frequency the power reductions provided by a tightly integrated solution become apparent. Figure three below identifies the power dissipations for a 4 transmit and 4 Receive system at 100 and 200 MHz when implemented in both discrete form, and within a RFSoC. This power saving becomes even more significant if scaled to an 8 transmit and receive solution.

Fig 3

Figure 3. Power Reduction provided by the RFSoC concept

However, it is not just board area and power where we benefit with the RFSoC concept, such a tightly coupled device also offers significant reductions in the complexity of sample clock distribution.  This provides a simpler clocking scheme, both at the device-level and also at the system level as the distribution network is less complex, as much is internal to the device.  This simpler clocking network reduces the power and cost associated with distributing GHz clocks on the PCB, offering a more efficient overall solution.  

The RFSoC concept therefore is capable of providing a more tightly integrated design which offers the potential for a reduced footprint and power dissipation. What remains is to examine the analog / RF performance of the ADC and DAC to ensure the required performance can be provided on the traditionally digital CMOS technology.

What analog performance can we achieve in advanced CMOS technology

Traditionally high performance analog circuits such as ADC and DAC have not used advanced CMOS technology for implementation. However, with digital assistance it is possible to implement high performance converters using 16 nm CMOS FinFET technology. This is the key which enables the RFSoC concept to be implemented (etal., 2017) (Christophe Erdmann et al., 2017). While the cited works present test chips and do not define the final performance of the RFSoC device, these initial test results warrant further discussion.

Two test chips were developed to examine the potential RF/Analog performance in such a technology. The first implemented a ADC and digital circuitry, while the second implemented a DAC convertor and its digital circuitry. The ADC test chip implemented a three-stage asynchronous pipelined SAR with open-loop integrator based amplifiers as shown in Figure 4.

Fig 4

Figure 4. (a) Overall Architecture (b) ADC Topology

This architecture was selected as it allows maximization of the sampling frequency, resolution and linearity. To ensure reduced power, noise and cost the architecture is supported by several dynamic circuits and multiple digital calibration loops. The ADC design is configurable to support either dual channel conversion using inputs In0 and In2, in Figure 4 at 2 GSPS, or a single channel conversion at 4 GSPS using In1. This approach is what enables the ADC to support either direct RF or I/Q architectures. However, using the 4 GSPS sampling rate provides more flexibility within the frequency planning as it supports a wider bandwidth. Each 2 GSPS ADC slice contains four 500 MSPS ADCs which operate in an interleaved manner. To address PVT and leakage issues impacting performance at low sampling frequencies, an asynchronous clocking scheme is implemented within the ADC.

The results obtained for this ADC test chip at 4 GSPS in direct RF mode are INL +/-1.5 LSB and DNL +/-0.3 LSB. While with applying an input of -1dBFS signal at 1.9 GHz the convertor provides a SFDR of 67.0 dB and SNDR of 57.3 dB while total power at 4 GSPS is 513 mW as shown in figure five.

Fig 5

Figure 5. INL, DNL, FFT and Power

The DAC test chip implements a mixing-DAC which provides full operation across the 1st, 2nd and 3rd Nyquist zones, this is enabled by implementing mixing within the data path. As with the ADC the DAC test chip implements a dual mode RF DAC with current steering outputs.

Fig 6

Figure 6. Dual Mode RF DAC Architecture.

Being designed with 5G applications in mind, the test chip DAC offers a ACPR of -70.8 dBc in a 20 MHz channel when centred at 5.2 GHz and a NSD of -160.2 dBm/Hz. When generating a 2-tone signal at 5.2 GHz in normal mode both IM3 is better than -71 dBc, while SFDR is 62 dBc in the first Nyquist zone.  While in mixing mode these become -65 dBc and 59 dBc respectively over the second Nyquist zone.

Fig 7

Figure 7. IM3 SFDR and Output Power

How does RFSoC address these challenges?

Addressing the challenges presented by 5G requires the capability implement systems which support increased spectral efficiency and ultra-densification. This requires as outlined the ability of the 5G radio to offer a low power, compact, high performance system. This solution also must also scale with the number of antenna to be supported.

The RFSoC concept address these challenges and more providing a significant reduction in the solution foot print to implement a small radio when compared to a discrete implementation of circa 50%. As the number of antenna supported by the system and signal BW increases so does the number of JESD links required between the SoC and the external convertors. This space saving becomes even more significant thanks to the integration of the RFSoC. This reduction in foot print enables the current proof of concept implementations to become more commercially viable.   Implementing a RFSoC approach also brings similar benefits in power reduction when compared to a discrete implementation.

Implementing the signal processing chain downstream of the ADC and DACs within the programmable logic can leverage high level synthesis. This enables high level languages such as C, C++, Matlab and Simulink to be used to capture the design and generate the design from the system model. This approach removes the need to define the system model, before implementing it within a HDL like VHDL or Verilog. This reduces not only the development time but also enables more efficient system design enabling the RF and baseband processing to work together as one to create an optimal implementation. Verification of the RFSoC will also be simpler as the digital and RF algorithm will be able to be co verified using the development flow.

The use of direct sampling and tightly integrated solution which provides both processors and programmable logic also enables flexibility in implementing the final architecture. This is increasingly important in a rapidly evolving domain such as 5G as the final specifications are not yet adopted and approved. This means late revisions to the standard can be accommodated prior to roll out, and future standard revisions can be implemented with greater ease in the field due to the re-programmable nature in the field.

Many of these 5G applications will be in remote and isolated locations as such the security provisions provided by the RFSoC such as anti-tamper features, secure boot and trust zone. Will ensure unauthorised personal cannot access and modify the operation of the radio. Similarly, the RFSoC provides advanced power management options which will allow the device to reduce its power consumption until it is needed. This will be very important in installations applications where 5G service is expected by the user but it is only used occasionally.


Addressing the challenges presented by 5G require a novel and disruptive approach this is provided by the RFSoC concept. This concept presents a tightly integrated software defined programmable solution which offers not only the performance required within the signal chain but also reduced implementation size and power dissipation along with scalability to support massive MIMO applications. Of course, it is not just 5G applications that the RFSoC concept is applicable to, it is also suitable for DOCSIS, Imaging and many other mixed signal applications.


Christophe Erdmann et al. (2017). A 330mW 14-bit 6.8GS/s dual-mode RF-DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz. ISSCC.

etal., B. V. (2017). A 13b 4GS/s Digitally-Assisted Dynamic 3-Stage Asynchronous. ISSCC.