Signal Integrity

Navigating Signal Integrity Challenges Transitioning from PCIe Gen6 to Gen7 Cover 2-20-24.jpg

Navigating Signal Integrity Challenges: Transitioning From PCIe Gen6 to Gen7

With PCIe Gen7 on the horizon, expected to debut around 2025 at a staggering 128 GT/s data rate and a pad-to-pad channel loss budget shift from -32dB at 16GHz to -36dB at 32GHz, this paper delves into the evolving performance requirements for Gen7 connectors and details the pivotal design changes needed to meet these demands. The study delves into meticulous design refinements in both the Add-in Card and Baseboard components, addressing challenges such as signal integrity concerns, ground-mode resonances, and the delicate balance between signal performance and mechanical reliability.


Read More
What is This Material Called FR-4 Cover.png

What is This Material Called FR-4?

Within the PCB industry, FR-4 materials have long been accepted as “standard” materials. However, their use was not specific to the types of board being designed. For today’s high-speed, high-frequency designs, careful engineering and material selection relative to the resin systems and glass weave styles needed will ensure that a product will work as specified, as designed, and as manufactured. In addition, the finish of the copper used in the signal and power layers also needs to be controlled in order to ensure that loss goals are met.


Read More
Alternative Approach to Analyzing Far-End Crosstalk 2-6-24.png

An Alternative Approach to Analyzing Far-End Crosstalk

Reducing various types of noise such as reflections, mode-conversion, return-path bounce, and crosstalk becomes a serious challenge in signal integrity designs of high data-rate interfaces. In this article, Dror Haviv focuses on the analysis and properties of the FEXT, presenting an alternative way to analyze the FEXT and its properties using the superposition theory of the differential signal and the common signal.


Read More
How Interconnects Work Anatomy of Crosstalk Cover 2-6-24.png

How Interconnects Work: Anatomy of Crosstalk

Crosstalk in PCB and packaging interconnects is arguably one of the most complicated phenomena that may cause signal degradation. Crosstalk effects can be treated statistically as a deterministic jitter with a bounded distribution, but the distribution is usually not known. A direct analysis of a worst-case crosstalk scenario may lead to a system overdesign. Neglecting it in design may cause a system failure that is difficult to find and fix later in a design process. Distortions caused by crosstalk cannot be corrected by signal conditioning techniques at a receiver side. It is very important to understand the sources of crosstalk, how to quantify it and how to mitigate it efficiently, as Yuriy Shlepnev demonstrates in this installation of the "How Interconnects Work" series.


Read More
The Road from 1 Gbps-NRZ to 224 Gbps-PAM4.png

The Road from 1 Gbps-NRZ to 224 Gbps-PAM4

Semiconductor signal conditioning and signal recovery innovations have extended data rates by managing allowable signal-to-noise ratio (SNR) at progressively higher Nyquist frequencies. We have experienced how each successive signaling technology increases the electro-mechanical design resolution needed to address the channel physics while respecting the SNR of the chips. These movements throughout the years have provided a baseline of traditional design goals that lead us to better understand today’s 224 Gbps-PAM4 physical layer requirements.


Read More