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We have to use enough capacitors so that the PDN functions properly. At the same time, to keep cost and size in check, we want to avoid overdesign and not use capacitors unnecessarily. Read on for advice on how to find the balance.

Get a basic EM understanding of resonant behavior, a method for quickly determining resonant frequencies, and a secondary set of metrics to evaluate if a frequency is excited or not.

The RFSoC concept does just that integrating the multi giga sample ADCs and DACs within the same silicon as the SoC, which contains the processing system and programmable logic. This offers a much tighter integrated solution providing the potential for both reduced footprint and power dissipation, while providing a direct sampling RF solution for 5G applications. Integration of ADC and DAC is not on its own sufficient to address the challenges.

Emerging 100 Gigabit Ethernet and 400 Gigabit Ethernet requirements for communication networks have put increasing demands on Internet infrastructure. New methods of design, validation, and troubleshooting to optimize high speed digital channels are being employed in the R&D laboratory. This article discusses new concepts for serial link design and analysis as applied to physical layer test and measurement techniques. Novel test fixtures and signal integrity software tools will be discussed in real world applications in the form of design case studies.

This is the first year that NIWeek has taken place in late May instead of its normal early August time slot and switches permanently to this part of the calendar. NIWeek 2017 kicked off with new CEO Alex Davern paying tribute to Dr. T with a standing ovation from the audience. Read this summary of what happened at NIWeek 2017.

Artech House announced the publication of High-Speed Circuit Board Signal Integrity, Second Edition by Stephen C. Thierauf.  This thoroughly updated leading-edge circuit design resource presents the underpinnings and practical guidance needed to analyze, investigate, and solve signal and power integrity issues.

This method enables designers to create 25+ GT/s vias quickly, deliberately, and with much less uncertainty than the traditional technique. Read on to find out more.