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Tektronix, Inc., introduced the 6 Series MSO mixed signal oscilloscope. The new oscilloscope extends the performance of midrange oscilloscopes to 8 GHz and delivers a 25 GS/s sample rate simultaneously on all 4 channels. A first for this oscilloscope class, while accommodating the needs of designers working on faster, more complex embedded system designs.

This spring, Molex and Samtec announced a collaboration on next-generation data center solutions. SIJ caught up with Brian Vicich of Samtec, Inc and Brent Hatfield of Molex to find out what that means for engineers.

In more than 30 years of teaching signal integrity, I find the most confusing topic for engineers, even those working in the field for years, is the question of what is the impedance of a transmission line?  Read on to learn about the 5 types of impedance.

Nanosecond-level clock synchronization can be an enabler of a new spectrum of timing- and delay-critical applications in data centers. However, the popular clock synchronization algorithm, NTP, can only achieve millisecond-level accuracy. Current solutions for achieving a synchronization accuracy of 10s-100s of nanoseconds require specially designed hardware throughout the network for combatting random network delays and component noise or to exploit clock synchronization inherent in Ethernet standards for the PHY.

SIJ talked with Dave Kohlmeier about industry trends, how to foster innovation, and what today’s EDA customers need most.

In high-speed digital channel design, vias are everywhere and are becoming very crucial elements to the channel performance. Especially with the higher data rate requirements in mobile, networking, and data center applications, the effect of vias in a design is very noticeable. Design engineers have traditionally used time domain reflectometry (TDR) as a tool to characterize and optimize via designs, yet the TDR approach comes with shortcomings such as demanding shorter rise-time step signal or larger bandwidth S-parameters, and inaccurate read-out on the via impedance.

In this article, we propose a simple and effective Z-input impedance method that augments the traditional TDR method for characterizing and optimizing via designs in much faster speed systems.

For this project, we will use an Atmel 328 microcontroller demo board, prepared with firmware to control it explicitly for our purposes, and with coaxial cables connected between the I/O pins and the input to the active probes of the scope. This interconnect provides a high bandwidth transmission line path for the signals.

If the die's I/O power rails are shared by the core power rails, here's a way to get your core power-rail measurements anyway.

How do you achieve high bandwidth in your measurements while minimizing current load on your DUT? Given that your DUT is a power rail, you really don't want to draw too much current from it., or your measurement system will distort the rail. But these two measurement criteria are at loggerheads with each other. It's a quandary, and it has to do with the fundamental nature of signals on interconnects.