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This DesignCon paper concentrates on the diverse abilities of AWGs to generate the signals required for compliance to standards such as HDMI 2.1, MIPI C-PHY, MIPI D-PHY, and MIPI A-PHY. Read on.
Incorporating the technique of using a quiet HIGH and quiet LOW I/O pin is a simple way of opening up a small window onto what is happening with the power rail of your die. Read on to have Eric Bogatin teach you how to implement it.
This paper first gives an overview of high frequency aliasing issues in context with industry standard compliance testing, then discusses the anti-aliasing algorithm. Read on.
This DesignCon 2022 paper presents a parametric ADC-based SerDes system modeling framework intended to support all project phases from architectural definition, through analog and digital design, to design validation.
This DesignCon 2022 paper focuses on the use of models for overall system validation, including both system models that evaluate the end-to-end link performance, and models used for individual block functionality to validate a mixed-signal design.