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The Challenge of Measuring a 40 µΩ (2000 Amp) PDN with a 2-Port Probe: The Measurement Result with Another VNA

In the final installment of this blog series, Benjamin Dannan, Heidi Barnes, and Steve Sandler continue their discussion of how to calculate the minimum CMRR with a PDN impedance measurement using a 2-port probe, demonstrating how to measure a sub-40 µΩ impedance when using an isolator that has sufficient CMRR using two different VNAs, the Bode 100 and E5061B. Achieving sub-40 µΩ impedance measurements is challenging, but completely realistic with the proper test equipment. 


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Understanding Burst Separation for DDR5 System Validation

DDR5 Electrical and Timing Measurement Techniques

In the final installment of his article series "DDR5 Electrical and Timing Measurement Techniques," Randy White explores how following a standard workflow for setting up thresholds and timings to distinguish bursts in DDR5 memory interfaces can make design validation much more efficient, ultimately ensuring compliance with specifications and improving system margin by identifying and resolving any issues, especially those related to either read or write transactions.


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