Power Integrity

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The Xpeedic EDA 2023 Suite includes 2.5D and 3D signal integrity and power integrity simulation for advanced packaging, along with three platforms to support 3D EM simulation, multi-domain co-simulation, and high-speed system simulation.

Inductance and resistance are fundamental to the design and analysis of Power Delivery Networks (PDNs). Excessive inductance and resistance can cause several severe power and signal integrity problems, as well as design failure. As we have seen, inductance can certainly be a confusing parameter. The type of the extracted resistance and inductance (loop or partial) depends on how the ports are connected to the model in the simulation. Consequently, their connection in the electrical circuit and the level of voltage details we can get from the simulation results will be determined. In many cases, it is required to know the voltage drop on the PWR path and on the GND path separately, therefore it is necessary to use partial inductances and resistances. The method of expressing SLI with partial inductances and the ideas behind it are briefly described in this paper.

Patented set of technologies unleashes GaN to operate at up to 20 MHz for the first time without overheating or RF issues, opening up a vast new application area for GaN.

In this article covering next-generation USB technology, Keysight reviews IP/PHY development kits, simulation solutions, and T&M solutions that serve as the foundation for silicon and system integrators to design compliant USB4 Version 2.0 products that meet strict interoperability requirements in the vast Type-C ecosystem.

For automotive and industrial applications, space-saving devices offer maximum working voltage of 1415 V in compact 2512 case size.

MM1200 provides high reliability, low resistance, and small footprint for medical, industrial, and test and measurement applications.

A VNA equipped with time domain analysis that includes basic and advanced window and gating functionality can help produce more accurate and repeatable impedance measurements. Read on. 

Many systems fail to live up to expectations, frequently because of an implementation failure at the breakout region. In this blog, Travis Ellis, SI engineer at Samtec, discusses connector-to-board transitions and common impairments to their performance.

Incorporating the technique of using a quiet HIGH and quiet LOW I/O pin is a simple way of opening up a small window onto what is happening with the power rail of your die. Read on to have Eric Bogatin teach you how to implement it. 

Modern ASIC-based systems can no longer be designed by rules of thumb when it comes to power integrity. In this DesignCon 2022 paper, Ben Dannan et al explain a workflow using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN.