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There was a time when the signal integrity of connections between digital ICs could be nearly ensured by following one simple rule: don’t connect more than some maximum number of input pins to any single output pin. Often the fanout limit would be around 7. No models, no simulations. Everything we needed was in the thick books of vendor datasheets that filled our shelves, the tree-killing viral precursor to AOL installation CDs. Ah, those were the days!

While a channel may pass a test, the remaining margin and thus its resilience against geometry or material variation in production may not be observable. However, such variations are critical because they may impede the performance or cause high volume manufacturing (HVM) products to fail. This coalition of authors has developed and demonstrated a polynomial chaos expansion (PCE) flow to analyze a full-featured 100GBASE-KR4 link starting from geometry specification to Channel Operating Margin (COM) margin at the receiver. Read on to see their award winning paper on the subject.

This detailed analysis offers a comparison of various calibration methods for pulse generators according to IEC/EN 55016-1-1 (CISPR 16-1-1), where the spectrum amplitude is measured using different methods and then the results are compared and the measurement uncertainty is determined.

Data converter based SerDes designs are gaining popularity due to their architecture flexibility as well as the capability to implement FFE through powerful DSP. This paper provides a theoretical analysis, realistic simulations and practical comparisons between TX side FFE and RX side FFE.

This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE,  DFE, and FEC equalization schemes for serial links at and above 112 Gbps.

This paper is a case study on causality problems in PDNs during power-aware SI simulations. It covers the causality of a PDN, and it reveals the impact on a design if a causality check is not done on the PDN for the package or board.

Since an oscilloscope and phase noise analyzer observe jitter differently, obtaining the same value from both instruments can be challenging. This article presents a phase-noise based methodology that provides similar values as time-interval error jitter derived from an oscilloscope.

I received a demo version of a new quick and easy TDR. I decided to take it for a test drive by measuring all the cables I had lying around my lab. The results were surprising!

The Electronic Design Innovation Conference and Exhibition (EDI CON) announced that this year, in conjunction with Microwave Journal (MWJ) and Signal Integrity Journal (SIJ), it will host an online, interactive event for high frequency and high speed design engineers on September 10-12, 2019. 

If performance matters, if the interconnects are not transparent, or if you want to develop good habits, you will want to incorporate these seven habits in your next two layer board design.