Items Tagged with 'pcie'

Spectrum's modular PCIe card family M2p is now completed and delivers cost-effective solutions for perfect tailored test systems.

We want to follow this mantra of 85 ohms for PCIe, but it may not be so easy. Here’s a look at exactly what the spec says, and what we can do about it.

In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.

Want to know more about the impedance and the encoding schemes adopted by prevailing high-speed I/O (HSIO) standards including PCIe, USB, Thunderbolt, and Ethernet? By looking back at the history of standards, some interesting trends and possible future directions are revealed.

While we all love increased network speed, there is an implied assumption that the backbone speeds of the internet will keep up with this rising demand placed upon it by millions of new 5G devices. PCIe 5.0 (or Gen5) represents the technology that is needed by the computer, data center, and ultimately the 5G wireless industry to enable the next generation of mobile and desktop applications. So, what is PCI Express 5.0 and how does it compare to PCI 4.0? Read on to find out.

PCIe Gen4 enables new wave of innovation to guide inner-loop SerDes optimization assisted by outer-loop system optimization. This paper introduces an outer-layer equalization scheme for managing SerDes inner-layer equalization to optimize overall system-level aggregate performance.