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This paper details a methodology of using multiple Huygens Boxes on the coupling path to predict RFI/desense at early design stage in mobile devices—all with an aim to minimize the RFI.
Architectural decisions depend on the ability to adequately analyze the link. This paper presents a methodology to model and evaluate the performance of both center and edge sampling schemes.
Interested in performance analysis for 100+ Gb/s per lane PAM4 interfaces? This paper takes a detailed look at high-speed serial link error propagation models and different Ethernet coding schemes as part of FEC performance analysis for 100/200/400 GbE systems with 100+ Gb/s per lane PAM4 interfaces.
Looking into advanced error code correction? Many techniques involve forward error correction. But what exactly is that and how does it relate to your design? Cathy Liu spells it out in this article.
While a channel may pass a test, the remaining margin and thus its resilience against geometry or material variation in production may not be observable. However, such variations are critical because they may impede the performance or cause high volume manufacturing (HVM) products to fail. This coalition of authors has developed and demonstrated a polynomial chaos expansion (PCE) flow to analyze a full-featured 100GBASE-KR4 link starting from geometry specification to Channel Operating Margin (COM) margin at the receiver. Read on to see their award winning paper on the subject.
This detailed analysis offers a comparison of various calibration methods for pulse generators according to IEC/EN 55016-1-1 (CISPR 16-1-1), where the spectrum amplitude is measured using different methods and then the results are compared and the measurement uncertainty is determined.
Data converter based SerDes designs are gaining popularity due to their architecture flexibility as well as the capability to implement FFE through powerful DSP. This paper provides a theoretical analysis, realistic simulations and practical comparisons between TX side FFE and RX side FFE.
This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE, DFE, and FEC equalization schemes for serial links at and above 112 Gbps.
This paper is a case study on causality problems in PDNs during power-aware SI simulations. It covers the causality of a PDN, and it reveals the impact on a design if a causality check is not done on the PDN for the package or board.