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Future data center and high-speed computation require faster connectivity to meet the increasing set of applications and bandwidth. IEEE and OIF have developed 106-112 Gbps per lane electrical interface specifications P802.3ck1 and CEI-112 G2 for the 400 GbE system. To meet the next-generation system bandwidth requirement, industry and standard bodies recently kicked off new projects aiming at 800 GbE or even higher speeds beyond 1 TbE. So what comes next beyond 112 Gbps for electrical interfaces over copper (Cu) channels? Will it be 224 Gbps?

The first available roughness models, such as Hammerstad, Hemispherical, Huray aimed to predict loss increase due to metal roughness. However, there was a problem. Read on to find out more.

Check out this article from Mike Hertz that details specifically how The Track measurement operator on oscilloscopes can be used to identify timing issues.

Signal integrity engineers almost always have to work with S-parameters. If you have not had to work with them yet, then chances are you will sometime in your career. As speed moves up in the double-digit GB/s regime, many industry standards are moving to serial link-based architectures and are using frequency domain compliance limits based on S-parameter measurements.

This simple measurement demonstrates the most important principle in SI/PI and EMI: that the return current will flow in the path of lowest resistance below about 10 kHz. But above about 10 kHz, the return current will begin to redistribute in the return path to be adjacent to the signal conductor. Read on to learn more.

In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.

Convergence in technology is not a new idea. The concept infers that disparate technologies evolve to a closer association or integration over time. Convergence occurs when any number of technologies, such as micro twinax cables, ASIC design, interconnects, advanced IC packaging, and others combine to offer a unique system-level solution. Many see convergence as required for 224 Gbps PAM4 system performance. 

The development of a low-noise emission PCBs is becoming more difficult because of higher integration densities, faster clock cycles, as well as integrating more radiators like wireless capabilities on to the IC. Based on these design challenges, it is essential to get all of the necessary information for the electric parts before they are placed on a customer’s PCB. Read on for advice on how to detect electromagnetic disturbances above ICs.

In the high-speed connector design arena, there are two opposing ideas. For some people, if you simply put pieces of plastic and metal together, eventually you have a signal transmission. This process is very simple. On the other end of the spectrum, there is the idea that a solid connector design requires a deep understanding of electromagnetic theory, a wisdom only sorcerers and wizards possess.

Read on for a way to combine a BERT and an oscilloscope for actual-time error detection and characterization.