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Power Delivery Network(PDN) time domain noise analysis is an essential part for SI/PI/EMI analysis, SIwave can utilize CPM’s current PWL file as a current sink for transient analysis combed with C4 bump’s RLC parasitics to give more realistic and accurate noise value.

SIPro uses an innovative new composite EM-technology that delivers high-frequency accuracy, together with the speed and capacity required for densely-routed cutting-edge PCB design. The PIPro solution is a collection of three PI-specific simulation engines for DC IR drop, AC power delivery network (PDN) impedance, and power plane resonances analysis.

This paper will present correlation data to validate the software and hardware tools necessary for fast-track deployment in upcoming PAM-4 applications.

In this paper we report results of IBIS-AMI based link analyses of realistic 56G PAM4 channels. Systems under investigation are represented by channel S-parameters and SerDes AMI models that capture actual chip designs, including impedance, equalizations and embedded tuning.

A quick overview of how to download and use Signal Integrity Design Using Keysight Advanced Design System (ADS) including examples.

Keysight ADS 2016 features a host of new, technologies designed to improve productivity, including two electromagnetic (EM) software solutions specifically created to help signal and power integrity engineers improve high-speed link performance in PCB designs. What follows is a listing of 8 ways in which ADS 2016 can help you, the engineer, overcome your signal and power integrity challenges.

In the beginning there was transient simulation. Ensuring functional chip-to-chip links in a system meant performing a time-domain simulation with a SPICE simulator. The result was a time-domain waveform that was evaluated during post processing for signal integrity (SI). The main task was to measure the eye diagram, usually assuming a perfect clock as the phase reference. Due to rising signaling speeds and decreasing timing margins, the task was made more challenging when it became necessary to account for other effects.

Which is better, tight coupled or loosely coupled differential pairs? How many decoupling capacitors should I use per power pin? Is 1 MHz enough bandwidth in my SSCG or do I need 3 MHz? Should I pay extra for ultra-thin dielectric in the power and ground planes? Will my channel still work if the channel impedance is 110 Ohms and not 100 Ohms?

There are many questions about measuring Power Delivery Networks (PDN), but these two are very common ones.  Why do we calibrate the 2-port measurement with a 1Ω shunt resistor and why do I use DC blockers on both ports?  In this article I’ll provide responses to both of these questions.  The measurement setup in Figure 1 is an example where I used both the 1Ω calibration and the inclusion of the DC blockers.

As systems designers work hard to squeeze more and more features into less board space, the power delivery paths are becoming increasingly complex. The current mature VRM designs based on Silicon MOSFETs are hardly meeting present day requirements. One of the promising technologies touted to solve this conundrum of space and performance constraints is GaN HEMT. However, many engineers are hesitant to design very high frequency GaN VRMs from the ground up. This paper evaluates the steps required to modify existing Si-MOSFET designs for use with eGaN HEMT devices. The paper also compares the expected performance of GaN vs. Si in linear and switching regulator topologies and covers some of the measurement challenges as well.