Items Tagged with 'PDN'

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The Challenge of Measuring a 40 µΩ (2000 Amp) PDN With a 2-Port Probe: The Measurement Result With Another VNA

In the final installment of this blog series, Benjamin Dannan, Heidi Barnes, and Steve Sandler discuss how to calculate the minimum CMRR with a PDN impedance measurement using a 2-port probe, demonstrating how is possible to measure a sub-40 µΩ impedance using a 2-port probe when using an isolator that has sufficient CMRR using two different VNAs, the Bode 100 and E5061B. Achieving sub-40 µΩ impedance measurements is challenging, but completely realistic with the proper test equipment. 


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What is Enough? VDDQ Package Power Integrity Analysis With a DDR4 PHY

As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all of your simulation models are correct. System designers typically assume that all of the vendor models are correct. So, what does an engineer do if one of the ASIC die models needed for a power integrity simulation is incorrect? 


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Contradicting the Common Belief: Decoupling Capacitors - Is More Always Better?

In the process of circuit design, electrical engineers must carefully position capacitors to decouple the power supply pins of integrated circuits (ICs). Yet, relying solely on a single capacitor for this purpose may potentially decrease the performance of the Power Delivery Network (PDN). Therefore, there exists a need for an elegant and systematic methodology in designing the PDN while utilizing a single capacitor. Within this paper, we analyze the single-capacitor scenario within the context of the PDN and introduce a systematic approach for its design. This approach not only suggests clear guidelines for when favoring a single capacitor over multiple capacitors is appropriate but also showcases that when these guidelines are exceeded, this method can be implemented recursively to achieve an optimal PDN solution.


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Data-Efficient Supervised Machine Learning Technique for Practical PCB Noise Decoupling

DesignCon 2023 Best Paper Award Winner

Design of PCB-based PDNs has become a challenge due to rising power consumption, lowering supply voltages, increasing integration density and design complexity. In this paper, we propose an algorithmic procedure using supervised machine learning techniques to provide expert guidance on the PDN design and optimize power supply decoupling capacitors. The proposed method replaces the computationally expensive numerical simulations with faster ANNs.



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Breaking Loop Inductance into Pieces

Inductance and resistance are fundamental to the design and analysis of Power Delivery Networks (PDNs). Excessive inductance and resistance can cause several severe power and signal integrity problems, as well as design failure. As we have seen, inductance can certainly be a confusing parameter. The type of the extracted resistance and inductance (loop or partial) depends on how the ports are connected to the model in the simulation. Consequently, their connection in the electrical circuit and the level of voltage details we can get from the simulation results will be determined. In many cases, it is required to know the voltage drop on the PWR path and on the GND path separately, therefore it is necessary to use partial inductances and resistances. The method of expressing SLI with partial inductances and the ideas behind it are briefly described in this paper.


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