Items Tagged with 'PDN'

ARTICLES

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How Ground Bounce Can Ruin Your Day

Low-speed printed circuit board (PCB) designs now have to deal with high-speed switching problems. This article examines the ground bounce generated from an LCD assembly while evaluating the impact of the ground bounce on the system level EMI. Three solution strategies to mitigate the ground bounce are analyzed, the pros and cons of each strategy are provided along with the test results.


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Why 2-Port Low-Impedance Measurements Still Matter

Measuring small resistance values is not trivial, but since 1861, when Lord Kelvin invented the Kelvin bridge,1 we at least have a solution for measuring very low DC resistances: the four-wire Kelvin connection (see Figure 1). We measure the resistance by sending a known current through the resistor and measure the voltage drop using separate wires.


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Target Impedance Is Not Enough

Target impedance has become a standard tool when designing a power distribution network (PDN). It establishes a limit to the highest impedance the power rail on the die should see looking into the PDN. If the PDN impedance stays below this limit, even the worst-case transient current from the die will generate an acceptably low rail voltage noise.


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VRM Modeling: A Strategy to Survive the Collision of Three Worlds

This paper reviews four levels of VRM models that VRM designers, board level interconnect designers, semiconductor designers, and product managers often use to explore design tradeoffs throughout the PDN system. The choice of which one to use involves considering engineers’ levels of expertise and what problems they expect to analyze. Some tradeoffs and relative merits of the models are described.


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