Items Tagged with 'PDN'

EM simulators that are optimized for PCB PDN simulations provide an increased level of automation to enable the basics of DC IR Drop, electrothermal, and AC impedance for early detection of design issues. In this article, Heidi Barnes, Steve Sandler, and Benjamin Dannan examine why the ability to optimize a PDN for Z_Target with PCB parasitics in the frequency domain and then export to an end-to-end PI Digital Twin simulation for validation in the time domain should be standard practice for the PI engineer.

Awarded the Best Paper Award at DesignCon 2024, this paper demonstrates that, for correlated data with PDN impedances in the sub-mΩ level, the impedance extracted from same-location top-bottom measurement can be significantly different from same-side adjacent via pair measurement, even if the physical separation is in the order of a mm

In this installment, Steve Sandler discusses measuring new ultra-low impedance PDNs using newly created usable test standards in the 20 µΩ range for accurate results.

This paper comprehensively addresses the numerous challenges presented when designing a power distribution network for a scalable 2000 Amp power supply and provides a complete process for designing, simulating, and validating a 2000 Amp core power rail. 

This article covers the importance of proper calibration, measurement, and de-embedding to ensure that the final capacitor model is free of errors, allowing an accurate representation of the PDN used in simulation. While capacitor models may play a seemingly minor role in the overall system design, the impact of capacitor models can significantly impact the system design and, importantly, design sign-off.

In the final installment of this blog series, Benjamin Dannan, Heidi Barnes, and Steve Sandler continue their discussion of how to calculate the minimum CMRR with a PDN impedance measurement using a 2-port probe, demonstrating how to measure a sub-40 µΩ impedance when using an isolator that has sufficient CMRR using two different VNAs, the Bode 100 and E5061B. Achieving sub-40 µΩ impedance measurements is challenging, but completely realistic with the proper test equipment. 

Having determined the amount of CMRR needed for 2-port measurement in the previous installment of this blog, Steve Sandler and  Benjamin Dannan return with a demonstration of how to create a DUT and make a 40 µΩ impedance measurement with the 2-port probe.

As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all of your simulation models are correct. System designers typically assume that all of the vendor models are correct. So, what does an engineer do if one of the ASIC die models needed for a power integrity simulation is incorrect? 

In the process of circuit design, electrical engineers must carefully position capacitors to decouple the power supply pins of integrated circuits (ICs). Yet, relying solely on a single capacitor for this purpose may potentially decrease the performance of the Power Delivery Network (PDN). Therefore, there exists a need for an elegant and systematic methodology in designing the PDN while utilizing a single capacitor. Within this paper, we analyze the single-capacitor scenario within the context of the PDN and introduce a systematic approach for its design. This approach not only suggests clear guidelines for when favoring a single capacitor over multiple capacitors is appropriate but also showcases that when these guidelines are exceeded, this method can be implemented recursively to achieve an optimal PDN solution.

This paper investigates via and trace coupling effects using measurements, hybrid, and full-wave solvers by de-embedding/calibration utilizing multiple test-boards.