Hardware engineers are learning the hard way that power integrity (PI) requires electromagnetic (EM) simulation of the printed circuit board (PCB) power delivery network (PDN). Traditional rules-of-thumb and leveraging data sheet examples are not an option as designs move from hundreds of Amps (A) to thousands. 1000 A across a 100 microhm (µΩ) PCB PDN is still 100 millivolts (mV) of IR drop and 100 Watts (W) of power dissipating as heat. This is one of the fundamental reasons for transporting power at a higher voltage and lower current for as far as possible. Less power lost in the path to the load. The other reason is impedance. Power rail voltage ripple is a direct result of dynamic di/dt currents interacting with the path impedance. When currents go up, the target impedance must go down to keep power rail voltage ripple within specified limits. Controlling the power delivery DC resistance and the parasitic path inductances of the PCB is a critical part of creating a Digital Twin model for designing a 2000 A PDN for a dynamic digital load.

Figure 1 shows an example of a 2000 A PDN design that Picotest uses to demonstrate their 2000 A 11-bit programmable transient load stepper.¹ This design was imported into a 3D-EM simulator to validate DC, electrothermal, and AC impedance design performance.

Figure 1. A topside picture of the Picotest 2000 A transient load stepper PCB is shown on the left. The PCB CAD date is imported into a full 3-DEM simulator to validate DC, electrothermal, and AC impedance performance.

What is Driving the Need for a PCB PDN EM Model?

To explain why the impedance of a 2000 A PDN is orders of magnitude harder than expected, one can combine the traditional target impedance equation with the need to minimize power. The PI engineer defines a target impedance so that a di/dt at any frequency, DC to GHz, will not result in exceeding the maximum allowed voltage ripple. The equation for target impedance is simply the maximum delta allowed voltage ripple divided by the worst case dynamic delta current change, as shown in Equation 1.

Combining this equation with the maximum available power provides an interesting look at the challenge PI engineers are facing. The relation between power and current can be estimated by the ideal DC-DC converter equation, where power in equals the power out, as shown in Equation 2:

where D is the duty cycle of the DC-DC regulator.

Here, D is less than or equal to 1, and shows how the current can be proportionally increased as the voltage is decreased with a point-of-load DC-DC converter while maintaining the same power level. If the allowed voltage ripple is set to 5% and the maximum delta current transient to 50% of the maximum current, then Equation 3 can estimate Z_Target as a function of voltage for a set power level:

Plotting Z_Target as a function of the DC/DC converter output voltage, D×V_in, while holding the power constant for a given application shows an exponential decrease in target impedance, shown in Figure 2.

Figure 2. A plot showing how target impedance decreases with the output voltage of a DC-DC regulator for a given application where the power is held constant. As the output voltage drops the current increases proportionally, but the target impedance decreases exponentially.

A USB design at 4.5 W and 5 Volts (V) has a target design impedance in the hundreds of milliohms (mΩ) and may not be impacted by PCB PDN path parasitics; however, if the voltage is dropped down to sub-1 V levels, then Z_Target can easily drop into tens of mΩ. Typical FPGA designs at around 34 W with a 12 V input power connector to the PCB quickly drop to a Z_Target of a few mΩ for the sub 1 V core power rail. Finally, for the new generation of AI and cloud compute chips running at 1600 W, the target impedance at 12 V is already a challenge at 1 mΩ levels. This helps to explain why 48 V power rails and higher are now showing up in electronic designs to reduce the impact of PCB path parasitics until the final point-of-load DC-DC conversion, where the 2000 A is needed. Running 1600 W on a sub-1 V power rail drops the design target impedance into the tens of µΩ.

Historically, SPICE simulations without PCB EM models have been used for designs above 100 mΩ. The concept of Z_Target and the need to include the PCB parasitics as an EM model became necessary as target impedances decreased to tens of mΩ. A typical PCB PDN with 5 cm between the voltage regulator module (VRM) and the load can easily have mΩ of DC path resistance and hundreds of pHs of inductance that can no longer be considered small in proportion to Z_Target. As Z_Target decreases from mΩ to µΩ, there is also an increasing demand for higher fidelity Digital Twin PDN simulations that include VRM behavioral models and worst case dynamic loads.²

How to Create the PCB PDN EM Model

Knowing that PCB EM parasitics are a critical part of designing a 2000 A power delivery network, the next question is how to create and use a PCB PDN EM model in a simulation. EM simulator tools like Keysight’s ADS with PIPro EM are optimized for multi-layer laminate PCB PDN simulations. The designs are imported from fabrication files like ODB++™ and IPC-2581™ with access to components, net names, and PCB stackups that allow for an increased level of automation when setting up a full 3D-EM analysis. EM models are needed for DC IR drop, DC Electrothermal, and AC impedance. DC IR drop models can quickly identify any asymmetries in the voltage delivery to large digital loads with hundreds of power and ground pins. Optimum locations for sense lines can be found, and layouts modified to maximize the uniformity of the power delivery. DC electrothermal simulations can help determine the amount of cooling required and the trade-offs between thicker copper layers versus adding more layers to prevent thermal run away and improve reliability (see Figure 3).¹

Figure 3. DC electrothermal simulation of the Picotest 2000 A transient load stepper showing the importance of water cooling to prevent thermal runaway.

AC Impedance EM models are a critical part of the Digital Twin PDN model that can simulate transient behavior to validate the pass/fail ripple voltages on the power rail. The PCB AC Impedance EM model can also be used to look at the spatial distribution of current densities over frequencies. The current density plots in Figure 4 show how the VRMs deliver power from the edges at low frequency, while the decoupling capacitors under the 512 load cells dominate at 10 MHz.

Figure 4. The 3D EM AC current density plots for the Picotest 2000 A transient load stepper show how the current delivery changes from the VRMs at 10 kHz to the decoupling capacitors under the load cells at 10 MHz.

The AC impedance model includes ports for the decoupling capacitors so values can be optimized to meet a desired Z_Target in the frequency domain. This decoupling capacitor optimization is best done before adding the EM model to the end-to-end PI Digital Twin simulation. To use the AC Impedance EM model in a PI Digital Twin simulation, it can be saved as an S-parameter behavioral model, as shown in Figure 5, with connecting ports to the VRM, the load, and passive components, such as decoupling capacitors.¹

Figure 5. The PCB PDN EM model can be exported as an S-parameter behavioral model.

How to Create the Switching VRM Model and Transient Load

The PI Digital Twin connection to the VRM needs to be a behavioral model of the VRM that can handle the large signal dynamic behavior of the DC-DC converter’s interaction with the load. Complete transistor level models of a VRM may work for evaluating set point characteristics, but when connected to real-world PCB EM models and dynamic loads, a transistor level simulation can fail to converge or take days to run. To get around this problem, the Sandler state-space-average (SSAM) VRM behavioral model can be used.³ This model captures the classic behavior of a switched mode power supply design including the feedback characteristics to create both small signal AC behavior and large signal switching transients. The reason for this type of behavioral model is that it can be run both in a traditional transient SPICE simulation, or in the frequency domain using harmonic balance (HB). HB is a powerful technique that simulates a circuit with enough harmonics of the fundamental frequency to convert the spectral data to the time domain using an iFFT. The benefit is that the HB simulation jumps directly to the steady state condition and avoids the longer simulation times required for a transient simulation to reach steady state. Running the switching model in both a transient SPICE simulator and the HB simulator shows that they get the same result (see Figure 6).⁴

Figure 6. The plots on the top show how a transient simulator must wait to reach steady state before the voltage ripple can be measured, while the bottom plots show how HB can simulate enough harmonics of the switching frequency to directly convert to stead state voltage ripple solution.

This SSAM VRM model can easily be paralleled together to represent the 55 phases of the VRMs
 each delivering ~36 A to reach a total of 2000 A for the Picotest 2000 A transient load stepper design (see Figure 7).

Figure 7. The modular design of the off-the-shelf VRMs allows paralleling the output phase to get to 2000 A. In simulation, all the phases are using the same VRM SSAM model.

The last step in creating the Digital Twin is to add the behavior of the load. This can include the passive S-parameter behavioral model of the package die PDN and a dynamic current I(t) of the load. Here, a switch model that can run in transient or HB is once again used to create a switching transient load at the desired frequency.¹

The Complete PI PDN Digital Twin

 The complete 2000 A PI Digital Twin model is shown in Figure 8

Figure 8. The end-to-end PI PDN Digital Twin with 55 VRM phases switching at 500 kHz, connected to a PCB PDN EM model and a transient 91 kHz switching load. The circuit uses an S-parameter simulator for PDN impedances and HB for steady state large signal transient ripple.

Simulating just the impedance helps to identify resonances with higher impedance that can lead to worst case power rail ripple if excited with a dynamic load. In this design, there is a peak in the impedance around 91 kHz (see Figure 9).

Figure 9. Simulating the PI Digital Twin in the frequency domain with the VRM on and off shows how the VRM controls the impedances below 30 MHz, and at 91 kHz there is an impedance peak indicating a resonance in the PDN.

This resonance is a result of higher than desired output impedance from the VRMs, and a limited amount of bulk capacitance. The desire was to push the performance of the VRM technology instead of spending more money and space for the bulk capacitors in this initial demonstration of the Picotest 2000 A transient load stepper.¹

Knowing that a dynamic load switching at 91 kHz can excite this resonance and cause a worst case voltage ripple, the 2000 A PDN Digital Twin is then run with this worst case 2000 A load being turned on and off at 91 kHz.² The 55 phases of the VRMs are all switching at 500 kHz with different phases to deliver the dynamic 2000 A current to the 91 kHz load. The HB simulator runs this full PI Digital Twin simulation in less than 77 seconds (see Figure 10).

Figure 10. The PI PDN Digital Twin simulates in 77s with all 55 phases of the VRMs switching at 500 kHz and the 2000 A transient load switching at 91 kHz.

The PI Digital Twin shows the corresponding undershoot (droop) and overshoot (kick) that occurs with the 2000 A load. Making design modifications with the PI Digital Twin that simulates in 77 seconds can build engineering intuition, save hours of engineering debug time on the bench, and mitigate expensive hardware failures.

Conclusion

Including the EM behavioral model of the PCB PDN parasitics is now a critical part of designing and validating a 2000 A PDN. The orders of magnitude drop in Z_Target from hundreds of mΩ to tens of µΩ is driving the need for higher fidelity PI PDN Digital Twin simulations that include a dynamic switching VRM model, the PCB PDN EM model, and a worst case transient load model to validate the design before fabrication. Behavioral VRM models like the Sandler SSAM and transient load switch models that run in HB have a significant simulation time savings advantage by jumping directly to the steady state results for fast optimization and debugging of a design. Digital Twin HB simulations can run in a matter of seconds or minutes compared to transient simulations, which can take hours or even days when including the PCB EM model. Creating the PCB PDN EM model also continues to get easier. EM simulators that are optimized for PCB PDN simulations provide an increased level of automation to enable the basics of DC IR Drop, electrothermal, and AC impedance for early detection of design issues. The ability to optimize a PDN for Z_Target with PCB parasitics in the frequency domain and to then export to an end-to-end PI Digital Twin simulation for validation in the time domain should be standard practice for the PI engineer.

Acknowledgments

A special thanks to the Research and Development team that keeps advancing the EDA simulation technology, John C. Moore, Robin Sercu, Marnik Brunfaut, Tim Boonen, Marwan Antoun, Oleh Kozynets, Hyoung Min Suh, Jan Vanhese, and Bram de Greve. A special thanks to Emma Duhrssen for keeping track of all the hardware pieces and enabling great things to happen.

REFERENCES

1. S. M. Sandler, B. Dannan, H. Barnes, I. Ben Ezra, and Y. Ni, “Design, Simulation, and Validation Challenges of a Scalable 2000 Amp Core Power Rail,” DesignCon 2024.
2. H. Barnes, J. Carrel, and S. Sandler, “A Method for Dynamic Load Current Testing with a Benchtop Power Supply,” DesignCon 2020.
3. S. M. Sandler, “Measurement Based VRM Modeling,” IEEE SPI 2017.
4. S. M. Sandler, B. Dannan, H. Barnes, and C. Yots, “VRM Modeling and Stability Analysis for the Power Integrity Engineer,” DesignCon, 2023.