The progression to higher data rates puts increasing demands on the design of practical SerDes channels. For 112 Gbps PAM4 signaling the PCB must be optimized for loss, reflections, crosstalk, and power integrity. This is especially true for silicon evaluation boards that show silicon  performance transparently while giving the customer maximum control over channel loading decisions. Such designs feature limited I/O count packages with short routing lengths, mated to minimal PCB interconnects and an RF cable solution such as Samtec’s Bulls Eye High-Performance Test System (Figure 1) .
The authors designed a silicon evaluation board (Figure 2) for our partner Alphawave with a loss target (TX lane) of 3 dB at 28 GHz including package, PCB, and 6” of BE70A cabling. Notwithstanding this tight insertion loss (IL) budget, we wanted to use cost-effective PCB materials that would demonstrate practical feasibility. We chose a 10-layer stack-up with Itera MT-40 dielectrics and VLP copper which included four routing layers, of which only two were required for the present evaluation topology. This is an aggressive cost point that posed challenges for via breakout optimization and for clean power distribution to the four separate BGA device rails.
A key design choice was to place the Bulls Eye block on the bottom side of the PCB to allow closer positioning to the device package. This eliminated conflict with keep-outs for mounting holes and resulted in PCB net lengths below 16 mm for the TX channels, each feeding an attached 6” compression mounted coax cable.
With the overall topology decided, the package and PCB interconnects were modeled in iterative design cycles to optimize signal integrity for loss, reflection, and crosstalk, using ERL (effective return loss) [3, 4] as the primary design metric.
Figure 1: Simplified model for package + PCB co-simulation
The active power components were placed away from the BGA load to provide flexible configuration (for example, using a lab supply instead of on-board regulation). This made power distribution a bit more difficult. With this caveat, we chose a quiet power topology using cascaded linear regulators.
We modeled bypass capacitor selection and placement to ensure good regulator stability and sufficiently low impedance to minimize load silicon supply noise. IR drop was a pressing issue. The minimal layer count prevented enough power/ground layers in the stack-up to support four fully isolated power fills. Moreover, tightly spaced BGA balls for these rails required power routing to be distributed where possible across several stack-up layers. To manage this, we ran iterative analyses to optimize current density per pin.
Figure 2: Powered evaluation board with Bulls Eye mounted opposite the test chip
While the finished evaluation platform showed excellent BER results (Figure 3), we didn’t quite hit the 3 dB overall channel target due to higher than expected package copper losses and the notable impact of the reflowed 0.6 mm solder balls. Figure 4 shows the relative IL contributions of package, PCB, and cable assembly. Of interest to designers will be the Bulls Eye BE70A series performance that incurs well under 1 dB loss at 28 GHz for a 6” cable reach.
Figure 3: 106.25 Gbps PAM4 Tx measured eye Figure 4: Channel IL breakdown
This article is a preview of the DesignCon 2021 paper, A Case Study in the Development of 112 Gbps-PAM4 Silicon and Connector Test Platform” scheduled to be presented on August 17th 2021 at 11:10am.