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A common design technique for power distribution networks (PDN) is the determination of the peak distribution bus impedance that will assure that the voltage excursions on the power rail will be maintained within allowable limits, generally referred to as the target impedance. In theory, the allowable target impedance is determined by dividing the tolerable voltage excursion by the maximum change in load current.

Power distribution networks (PDNs) delivering power to ICs in a system need to be thoroughly designed and analyzed in order to make sure any voltage fluctuation on the rail is within the tolerance of every IC connected to that rail.  As ICs on the rail draw power, they generate a voltage fluctuation on the rail.  The PDN must have the capacity to supply enough charge such that the resulting voltage drop is less than the maximum voltage drop each IC on the rail can tolerate.  If voltage fluctuations appear outside IC tolerance limits, a slew of problems can surface such as IC damage, failure, or reduced lifespan.

DesignCon has been a tremendous source of information for myself and for the team I have been working with at SUN Microsystems, which later became part of Oracle Corporation. This summary is an attempt to capture some of the most influential papers from the past twenty years that made the biggest impact on our work.

This article presents a method for power integrity analysis in FPGA systems by configuring the FPGA to function as a vector network analyzer (VNA) test instrument for its own power distribution network (PDN).

It’s what you don’t know you don’t know that can ruin your day. This paper notes in detailed examples that with today’s high-speed designs, we can no longer restrict our thinking in terms of signal integrity, power integrity or EMC alone. We must consider all three disciplines and become educated about each of them to achieve successful designs.

This article discusses some of the common SI and EMI issues that can be found using DRCs.

This method enables designers to create 25+ GT/s vias quickly, deliberately, and with much less uncertainty than the traditional technique. Read on to find out more.

Low power, high performance circuits are often plagued by power supply related issues.  This common occurrence is frequently due to mythical (or misapplied) rules-of-thumb.  These rules of thumb often lead us in the wrong direction, making things worse rather than better.  In this article, I’ll highlight some of the most common mistakes engineers make and share some fundamental rules for designing clean power for sensitive circuits.  Applying these rules will result in higher performance, lower cost designs with fewer design iterations.

We analyze the computational procedure specified for Channel Operation Margin (COM) and compare it to traditional statistical eye/BER analysis. There are a number of differences between the two approaches, ranging from how they perform channel characterization, to how they consider Tx and Rx noise and apply termination, to the differences between numerical procedures employed to convert given jitter and crosstalk responses into the vertical distribution characterizing eye diagrams and BER. We show that depending on the channel COM may potentially overestimate the effect of crosstalk and, depending on a number of factors, over- or underestimate the effect of transmit jitter, especially when the channel operates at the rate limits. We propose a modification to the COM procedure that eliminates these problems without considerable work increase.