Throughout a SerDes IP development cycle, multiple SerDes system models at different levels of abstraction are required to guide development. First, a simplified system model is used for architectural exploration and to derive specifications for the main SerDes blocks. Then, a detailed system model is developed to capture main design aspects, and to evaluate design tradeoffs between blocks. This model is frequently populated with analog simulation data for correlation purposes, as analog design information becomes available. Finally, to support mixed-signal design validation, the behavior of analog blocks is captured in SystemVerilog models with circuit-representative interfaces. Very often, these three sets of SerDes models are developed by different parts of the development team, requiring some level of correlation, which, in turn, increases IP development overhead.

At the same time, two system modeling options are available to facilitate technical interaction between SerDes IP suppliers and system integrators. First, at the project onset, channel operating margin (COM) tool can be used to achieve high-level specification alignment. This alignment could be either within the context of communication standards, or outside standards for proprietary links. Communication standards, which use COM as a channel compliance tool, effectively define high-level SerDes performance guidelines in the form of a reference SerDes model and its parameters embedded in COM. Proprietary links can also leverage the COM reference SerDes to define performance targets. Then, as the SerDes IP development approaches completion, correlated IBIS-AMI models drive signal integrity (SI) simulations, which are typically performed by the system integrators – the IP consumers. IBIS-AMI models expose SerDes performance while obfuscating the implementation details within the IBIS standard constraints; hence, SerDes IP suppliers usually maintain IBIS-AMI development and correlation as stand-alone customer-facing efforts.

Between the COM-driven specification alignment and the IBIS-AMI-driven SI sign-off, however, simulation-based technical interaction between the SerDes IP providers and the system integrators is challenging due to the lack of adequate SerDes system models. The COM reference SerDes model lacks implementation-specific details and time-domain analysis capabilities; while the IBIS-AMI models limit system observability and require substantial update efforts. Hence, neither COM nor IBIS-AMI modeling options are sufficient to fully support SerDes providers and system integrators during their respective circuit and channel design phases.

In leading-edge high-speed serial link systems, the SerDes circuit development is frequently concurrent with the channel development, opening an opportunity to co-optimize the circuit and the channel designs for early standard-compliant systems, as well as for the proprietary links. At first glance, the detailed design-representative system model seems like a good candidate to facilitate this circuit–channel co-optimization. However, IP protection concerns along with model support logistic challenges typically prevent IP suppliers from sharing their internal system models with system integrators.

This paper presents a parametric ADC-based SerDes system modeling framework intended to support all project phases from architectural definition, through analog and digital design, to design validation. Furthermore, this modeling framework fills the gap between the generic COM and correlated IBIS-AMI models, enabling SerDes IP suppliers to provide high fidelity models to system integrators, earlier in the customer’s system level design flow. This, in turn, enables simulation-based co-optimization between components of the serial link system.

We first introduce modeling techniques that enable a single model to support a wide range of system modeling activities. The parametrization of key design variables allows for the evaluation of a broad set of architectural solutions at the project onset, and to converge quickly on block-level specifications, facilitating the design phase. Decoupling relatively stable block interfaces from evolving block implementations enables a simulation-ready top-level system model at all times, while the underlying block-level implementations evolve to reflect the design’s progress. We use object-oriented modeling to achieve this interface-implementation decoupling. The object-oriented approach also enables model obfuscation at the block level for IP protection when sharing the model with system integrators. The block-level models support automated export to C-code or stand-alone executables. This is accomplished via a minimal dependence on simulation environment solvers, facilitating mixed-signal design validation through auto-generated SystemVerilog behavioral models of analog blocks. Then, we describe a correlation example to illustrate how the proposed modeling framework can be configured to mimic a silicon correlated IBIS-AMI model for a 112 Gbps ADC-based SerDes product.

The remainder of this paper is organized into six sections. Section 2 reviews typical system modeling activities through a SerDes IP development cycle, highlighting inefficiencies associated with maintaining multiple system models. Then, Section 3 outlines modeling techniques that enable a development of a unified SerDes modeling framework. Sections 4 and 5 present unified parametric transmitter and receiver models intended to support all internal SerDes development needs, and to augment customer-facing system modeling needs. Sections 6 describes a correlation example between the proposed SerDes model and an IBIS-AMI model of a 112 Gb/s ADC-based SerDes product, focusing on a customer-facing use case. Finally, Section 7 concludes this paper.

The paper referenced here was presented at DesignCon 2022. To read the entire DesignCon 2022 paper, download the PDF.