“Crosstalk” occurs when energy in one signal (called an “aggressor”) couples onto another signal (the “victim”), adversely affecting the victim signal’s performance. The aggressor/victim language associated with crosstalk indicates danger is lurking, provoking hardware engineers to constant vigilance. How can we tame this foe? Or, more specifically, what causes crosstalk? When does it become problematic? What can you do to ensure it does not ruin your product design? I’ll answer those questions in a moment, but first let’s have a look at the crosstalk issue I most often find and correct in today’s designs.
The Most Common Crosstalk Issue
As design tools and practices have matured, the most common crosstalk issue that escapes a design team’s notice is vertical layer-to-layer coupling. While solid planes are used to prevent this, voiding in these planes places small holes that signals can couple through. In my experience, these “Z direction” couplings are not found by design rule checks, and it requires only a small amount of vertical coupling to collapse and eye. This issue is growing because connector and capacitor pads are increasingly of a relevant feature size [RFS, 1] that must be impedance matched. More holes, more chances for coupling.
Figure 1 quantifies the impact of vertical layer-to-layer crosstalk on PCIe Gen3 eye height when a ground shield layer is not in place. The eye diagrams in Figure 1 show performance without crosstalk (left) and with crosstalk (right). Because the link is short (3”), the signals are over-equalized, and hence four voltage levels are seen (yes, this happens quite often ). With no crosstalk, the eye opening is ample at 150 mV. With crosstalk, each of the four voltage levels are widened by ~150 mV of noise, closing the eye. Simulated eye heights are plotted in the graph, revealing how eye height decreases as the amount of coupled parallelism between the layers increases from 0 to 200 mils on the X axis. As the “gap” distance between the layers decreases (gold=10 mils to red=4 mils, in 2 mil increments), eye height decreases at the rates shown in the color-coded boxes. These curves are easily created in Signal Integrity Toolbox™, so try out this exercise on your design using a free trial of the software.
Figure 1. Inter-Layer Crosstalk on PCIe Gen3 Eye Height, versus Layer Gap and Coupled Length (plots created in MATLAB and Signal Integrity Toolbox)
Figure 1 reveals inter-layer crosstalk can cause a 1 mV decrease in eye height per 1 mil of coupling when the layer-to-layer gap is 6 mils (blue). That means only 100 mils of parallelism can remove a generous eye margin. So, make sure diff-pairs do not overlap through gaps in ground planes – which typically must be done as a manual/visual process. That said, let’s take a step back and explain both the sources of crosstalk and the design methods that prevent it.
The Mechanics of Crosstalk
Over the years technology has worked against us causing typical (unmanaged) crosstalk voltages to increase from 2% to 30%, as shown in Table 1. As data rates increase and voltage margins decrease, even the smallest, unexpected signal disturbance becomes problematic – even just a few millivolts. As such, it’s important for engineers working in all aspects of electronics design and production to have a basic understanding of the mechanics of crosstalk.
Table 1 lists the factors that contribute to crosstalk. Intuitively, the closer the signals are to each other the greater their potential for coupling or crosstalk. As signals travel “close” together over increasing length (referred to as “parallelism”), the amount of crosstalk increases to the point of “saturation;” at saturation the maximum amount of crosstalk has been reached. As shown in Table 1, modern technology saturates very quickly so we don’t think about this as much as we used to. Crosstalk also grows with both voltage swing and rise time, or with increasing dv/dt and di/dt. In terms of the familiar equations, I=C*dv/dt and V=L*di/dt, capacitance increases as metal moves closer together and so does mutual inductance – and hence all factors continue to combine and increase crosstalk. As such, controlling signal spacing (and, if possible, voltage swing and edge rate) directly impacts the magnitude of crosstalk in your design.
Table 1. Factors Contributing to Crosstalk, then and now.
To understand how the factors interact and which factors are dominant, try entering the values in Table 1 into this on-line crosstalk calculator  (H=10 mils, h1=h2). Modify the parameters and observe what changes – this will enhance your crosstalk intuition. Perhaps try out the values inherent in your design.
Surprisingly, despite this increase in crosstalk potential, we have seen an overall decrease in issues. How can that be? Like other design challenges, the technology world rallied with awareness of the problem, designed rules to prevent it, and designed tools to ensure those rules are followed. So, before we panic, let’s put crosstalk problems into perspective.
Crosstalk in Perspective
Yes, crosstalk problems are real, but you might be surprised to learn I’ve encountered only three serious issues in 40 years – designing all types of electronic products. All three issues were found after hardware was built and fueled new disciplines in preventing crosstalk problems prior to implementation. As the issues are instructive, let’s take a look at what caused them.
As stated previously, the leading cause of system-level crosstalk failures is unshielded layer-to-layer parallelism in the Z (vertical) direction. Indeed, this caused two of the three problems. One was a long section of parallelism between a “high-speed” signal and a “low-speed” signal (watch out for this, “low-speed” signals don’t get enough attention anymore). The other problem involved two serial links signals with only 100 mils of coupling through plane cutouts. Both problems were extremely difficult to isolate, with the “aha” moments occurring during a careful study of layer-to-layer PCB layout artwork. While layout tools may assert they DRC (design rule check) these situations, I still visually overlay and examine adjacent layers for potential issues – particularly around cutouts. This is a situation where brainpower and experience surpass the capabilities of computer algorithms.
The third crosstalk issue was in package-level bond wires caused by interleaved inputs and outputs buffered within the IC. Crosstalk induced the inverse of the output back onto the input, and the resulting oscillation was so powerful and predictable I applied for a patent on this novel oscillator design. Who says problems can’t become inventions?
Because crosstalk problems are difficult to isolate and correct in hardware, and hence severely impact a product’s performance and schedule, majority of engineers simply design it out – albeit with increasing material cost. The exception to this might be very high-volume products; these design teams use detailed simulations and manual layout to minimize cost. But again, most product implementation teams simplify and solve the crosstalk problem by using design rules.
Crosstalk Design Rules
Crosstalk design rules reduce crosstalk to acceptable levels by managing the two directions in which signals can couple within a PCB: vertical and horizontal. Vertical crosstalk is caused by signals on other layers, or “inter-layer.” Horizontal crosstalk is caused by signals on the same layer, or “intra-layer.” Crosstalk from each direction is handled in different ways, as follows:
Inter-layer crosstalk problems are prevented by placing solid ground planes (shields) between signal layers. Although adding layers adds cost, solid planes solve numerous SI problems such as controlling trace impedance, return current, power supply impedance, and bypass capacitor loop current. So extra ground layers are readily added in all but the highest volume products. This sounds simple enough but be advised that a “solid” plane never exists in practice. As such, I’ll stress again it’s important to verify that signals will not couple through cutouts, antipads, or other gaps in the plane. In these areas, signals on both sides of the “shield” remain susceptible to crosstalk because part of the shield has been removed.
Intra-layer crosstalk is prevented by enforcing a spacing distance between signals greater than 5h to 7h, where “h” is the distance between the signals and their adjacent ground plane(s). The design rule is stated in terms of “h” to ensure the signal’s coupling to a nearby plane (which is good) is roughly an order of magnitude greater than its coupling to a nearby signal (which is bad). In practice, this generally requires signals to be spaced about 25 mils apart.
To illustrate the efficacy of the “5h” design rule, Figure 2 shows a crosstalk signal-to-noise ratio on the Y axis versus the spacing distance “D” between two signals on the X axis. As the Y axis is a ratio (not detailed here), larger values are “good” and smaller values are “bad” as shown. The colors show “h” (the stripline trace’s distance to ground in each direction) varying from 3 mils (red) to 7 mils (black), in 1 mil increments. The horizontal line marks a constant magnitude, which is the D=5h location for all values of h. For example, the h=3 mil line (red) crosses the horizontal line at 15 mils, the h=4 mil line (blue) crosses at 20 mils, and so on. While minor non-linearity is seen with small h values, the plot demonstrates how the design rule achieves a consistent crosstalk ratio across a variety of stackups and implementations.
Figure 2. Intra-Layer Crosstalk Magnitude versus Signal Spacing and Distance to Ground.
Figure 2 illustrates both how signal quality increases (i.e., decreasing crosstalk) as spacing between signals increases (larger D), and how an acceptable crosstalk level can be reached sooner if signals are closer to ground (smaller h). Again, manipulating “D” and “h” is the primary mechanism for controlling intra-layer crosstalk. Consult the design guidelines associated with your components or technology to determine the recommended D/h ratio; I expect you’ll find it to be in the in the 5 to 7 range, unless a constant D is used instead.
As stated previously, automated layout tools are better at enforcing intra-layer than inter-layer spacing rules. As such, ground shields are typically used vertically, and spacing rules are used horizontally. In rare situations, ground moats have been used horizontally and spacing rules are used vertically, and the physics involved is similar to that described above.
While it’s best to prevent problems before they happen, when confronted with crosstalk in hardware don’t forget you likely have programmatic control over SerDes/DDRx drive strength, edge rate, and equalization. You may find you can fix the problem using software . For example, simply turning off the Tx equalization shown in Figure 1 can restore the eye – even without removing the crosstalk.
Crosstalk problems can be real yet are not necessarily as pervasive as one might expect as long as design best practices are followed. Here we’ve discussed the factors that exacerbate crosstalk and how to manage them using design rules. Crosstalk simulation is used to develop physical design rules that are simple to implement, and also to cross-check and adapt the rules for a specific PCB when lowest cost is desired.
This article is an excerpt from Donald Telian’s book “Signal Integrity, In Practice.” A Practical Handbook for Hardware, SI, FPGA, and Layout Engineers.
 Telian D. (2022 April 1). ‘Which Discontinuities are Small Enough to Ignore?’ Signal Integrity Journal RSS.
 Telian D. (2022 May 3). ‘Fixing Signal Integrity Issues in Software.’ Signal Integrity Journal RSS.
 (2022 September 29).“Stripline Crosstalk Calculator.” EEWeb’s PCB Tools.