Technical Articles

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This paper proposes a model that can serve as a tool for evaluating FEC choices in 200+ Gb/s applications. It allows the comparison of the effect of different inner/outer codes and inner-FEC interleaving schemes on post-FEC BER. It can also be used as a tool for system-level transceiver design, allowing designers to see the impact of design choices on the post-FEC BER efficiently.

Inductance and resistance are fundamental to the design and analysis of Power Delivery Networks (PDNs). Excessive inductance and resistance can cause several severe power and signal integrity problems, as well as design failure. As we have seen, inductance can certainly be a confusing parameter. The type of the extracted resistance and inductance (loop or partial) depends on how the ports are connected to the model in the simulation. Consequently, their connection in the electrical circuit and the level of voltage details we can get from the simulation results will be determined. In many cases, it is required to know the voltage drop on the PWR path and on the GND path separately, therefore it is necessary to use partial inductances and resistances. The method of expressing SLI with partial inductances and the ideas behind it are briefly described in this paper.

Copper foil and oxide roughness are also major drivers of insertion loss behavior. As discussed in Part 1 of this article series, the first crucial step to efficacious design and development is understanding how the dielectric material attributes are to be carefully considered when assessing impedance and insertion loss performance. This article by Keshav Amla highlights the importance of considering roughness attributes in this assessment, ensuring a well-rounded approach to addressing impedance and loss, as well as skew, a signal integrity concern of ever-increasing importance.

This article series by Keshav Amla of Avishtech provides an introduction and overview of the dielectric materials upon which a PCB is built, focusing on what comprises these materials; the data available from the materials vendors; how the key material attributes drive performance; and how these ideas can be leveraged in the development of new product implementations.

In preparation for 224 Gb/s and beyond, Samtec engaged in a research project to characterize the transmission performance of emerging PCB material sets. Brandon Gore explores the current state of the art for PCBs and cables, comparing them and assessing the technology gap to fully support the insertion loss performance required for higher data rates.

In this article, Kella Knack outlines the stackup process, highlighting the importance of taking material issues, structural issues, and performance factors into account from the beginning of the design process. Knack discusses how providing fabricators with proper design documentation that includes precise information enables them to build to specification, ensuring correct functionality while avoiding additional costs for design.

Reduction of microstrip FEXT plays an important role in microwave engineering, as microstrip coupled line backward couplers suffer from poor directivity when not compensated. In this article, Henning Mextorf presents a general approach to improve directivity which does not require a modification of the dimensions of the coupled line structure and provides closed form solutions for optimum capacitor values.

In this article covering next-generation USB technology, Keysight reviews IP/PHY development kits, simulation solutions, and T&M solutions that serve as the foundation for silicon and system integrators to design compliant USB4 Version 2.0 products that meet strict interoperability requirements in the vast Type-C ecosystem.

PCB connector suppliers are often tasked with providing connectors that meet today’s high-speed and high-density requirements. In many cases, these connectors also need to maintain signal integrity under harsh conditions. Such models make it possible to simulate how the connector will interface and perform in its surrounding environment. IEH has partnered with Modelithics to offer 3D geometry models for various IEH hyperboloid connector products.

In this article, Bert Simonovich explores how to avoid “garbage in, garbage out” with field solvers by building an understanding of the nuances of PCB fabrication processes, the interpretation manufacturers’ data sheets, and the tool’s user interface.