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As you know, "us", Signal and Power Integrity Engineers, are full of tricks, rules of thumb, and shortcuts. These tricks mostly help us understand something, save analysis time and, why not, make us look smarter than we really are!! In that vein, seldom have I encountered a quick and dirty trick as useful and underestimated as S-parameter renormalization.
This month on the Signal Integrity Journal, we are taking a closer look at the new materials options for enhanced SI or PI performance. I recently asked Martin Cotton, director of OEM technology for the Ventec International Group, how his company saw the new materials opportunities for designers.
Differential clock and timing devices are commonly characterized for phase noise using baluns. While deceptively simple to use, baluns perform a fairly complicated process that can unknowingly introduce artifacts into measured results. This article describes such artifacts, discusses why they appear and how to eliminate them. Recommendations are provided for selecting a balun and using it to accurately characterize devices for phase noise.
Like any good tradesman, every electronic design engineer should carry a variety of tools in their toolbox. Some of the tools I like to carry are transmission line equations.
In many measurements, connections to the Device Under Test (DUT) is very important and can fundamentally determine whether the data we get is correct or not, whether the result is useful or potentially misleading. This article highlights some of the main items to consider. To illustrate the points, we use examples with DC-DC converter evaluation boards.
In this paper, we introduce a special class of resonant structure - the Beatty Standard - along with other classic resonators. We examine closely the resonant Beatty Standard, its impedance profile, loss characteristics, and its application to printed circuit board material property extraction. Suited for 32 Gbpsec simulation requirements, the Beatty Standard not only provides engineers a compact structure to perform material property extraction, but also help with establishing a robust design flow.
Many engineers are familiar with the Bode plot as an effective stability assessment method. However, some authors suggest and even teach that the Bode plot is the only method needed. This article shows why this thinking is short-sighted. A single, low cost instrument that can produce Bode plots, as well as two other stability assessment methods is discussed providing a more comprehensive stability assessment set of guidelines.
When we think of PDN, the first images that usually come to mind are FPGA’s and CPU’s. These circuit generally require ultra-low PDN impedance in order to maintain the appropriate voltage at the FPGA or CPU during the large dynamic current variations these devices present.
This study focuses on a much smaller scale addressing a very simple circuit comprised the related PDN issue. While the issues shown here may seem obvious to some, this is an excellent example of what is a very common problem.
In this paper we report results of IBIS-AMI based link analyses of realistic 56G PAM4 channels. Systems under investigation are represented by channel S-parameters and SerDes AMI models that capture actual chip designs, including impedance, equalizations and embedded tuning.
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Like any good tradesman, every electronic design engineer should carry a variety of tools in their toolbox. Some of the tools I like to carry are transmission line equations.
