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The current trend for many application requiring data converters is to get closer and closer to a full SDR (Software Defined Radio) system. While SDR architecture brings many benefits in terms of flexibility and SWaP-C (Size, Weight, Power and Cost) it often translates into higher bandwidth capability and is directly linked to the data converter sampling speed with the Shannon-Nyquist theorem.

No matter how well you understand the design principles, and no matter how much experience you have in designing boards, it’s easy for some problems to slip through the cracks because you just forgot to check that feature, or your design is just too big to manually check. This is where a design rule checker comes in.

The IEEE P370 standards group was formed over four years ago to draft a standard for the Electrical Characterization of PCB interconnects up to 50 GHz. On Monday, Jan 30, 2018, more than 30 engineers attended the organization’s first “plug fest” at the Santa Clara Convention Center to exercise some of the features of the proposed standard.

At DesignCon 2018, the IEEE P370 standards group announced the release of two important tools to assist all engineers for de-embedding. In the presentation by Jason Ellison and Heidi Barnes, “A NIST Traceable PCB Kit for Evaluating the Accuracy of De-Embedding Algorithms and Corresponding Metrics”, the two new tools were announced, a board kit and a de-embedding software tool.

Blando’s presentation illustrates the value of never accepting a result if it is not consistent with your engineering judgement. The determination of Blando’s team to resolve this simple problem benefits all of us to enable better differential pair measurements.

In our first electrical engineering class, we learn that the voltage across an inductor is L di/dt. We are ingrained with the idea that the voltage across an inductor is generated by the changing current through it. Not so, says Larry Smith, industry Power Integrity expert from Qualcomm and member of the SIJ EAB.

Now in its fourth generation, which sports data-transfer rates up to 16 Gb/s, Peripheral Component Interface Express standard (PCI Express, or PCIe) requires challenging physical-layer test requirements (Figure 1). We've covered electrical compliance test for PCIe 3.0 in some detail, but with the test specifications for PCIe 4.0 rounding into shape, it's time for a deep dive into electrical compliance test for this ubiquitous peripheral interface protocol.

January 24, 2018 (Norwood, Mass.) – Signal Integrity Journal, a sister publication to Microwave Journal covering signal integrity, power integrity and EMC/EMI related topics, has published its first printed magazine issue. Signal Integrity Journal was launched in September 2016 as an online magazine, and is now celebrating its success with this 2018 print edition (which is also available as a digital e-book).

DesignCon has been a tremendous source of information for myself and for the team I have been working with at SUN Microsystems, which later became part of Oracle Corporation. This summary is an attempt to capture some of the most influential papers from the past twenty years that made the biggest impact on our work.

This article presents a method for power integrity analysis in FPGA systems by configuring the FPGA to function as a vector network analyzer (VNA) test instrument for its own power distribution network (PDN).