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Serial peripheral interface (SPI) is one of the most widely used interfaces between microcontroller and peripheral ICs such as sensors, ADCs, DACs, shift registers, SRAM, and others. This article provides a brief description of the SPI interface followed by an introduction to Analog Devices’ SPI enabled switches and muxes, and how they help reduce the number of digital GPIOs in system board design.

I have lost count of the number of times I have been asked to fix an EMC problem, only to find that a shielding box has been designed or purchased to provide XdB up to fMAX. Or a filter has been designed or purchased with a similar specification, but to reduce cost the filter has been mounted on a printed circuit board (PCB) inside the box, with a cable from it entering or exiting the box through a plain connector.

SIJ talked with Martin Stumpf about industry trends, how to foster innovation, and what today’s designers need most from their test equipment.

Here’s a look at how phase noise converts to time-interval error jitter, which is particularly important to those working on reference clocks for high-speed SERDES or sampling clocks. Read on to see how this can help debug systems to reduce sources of timing noise.

This spring, Molex and Samtec announced a collaboration on next-generation data center solutions. SIJ caught up with Brian Vicich of Samtec, Inc and Brent Hatfield of Molex to find out what that means for engineers.

In more than 30 years of teaching signal integrity, I find the most confusing topic for engineers, even those working in the field for years, is the question of what is the impedance of a transmission line?  Read on to learn about the 5 types of impedance.

Nanosecond-level clock synchronization can be an enabler of a new spectrum of timing- and delay-critical applications in data centers. However, the popular clock synchronization algorithm, NTP, can only achieve millisecond-level accuracy. Current solutions for achieving a synchronization accuracy of 10s-100s of nanoseconds require specially designed hardware throughout the network for combatting random network delays and component noise or to exploit clock synchronization inherent in Ethernet standards for the PHY.

SIJ talked with Dave Kohlmeier about industry trends, how to foster innovation, and what today’s EDA customers need most.

In high-speed digital channel design, vias are everywhere and are becoming very crucial elements to the channel performance. Especially with the higher data rate requirements in mobile, networking, and data center applications, the effect of vias in a design is very noticeable. Design engineers have traditionally used time domain reflectometry (TDR) as a tool to characterize and optimize via designs, yet the TDR approach comes with shortcomings such as demanding shorter rise-time step signal or larger bandwidth S-parameters, and inaccurate read-out on the via impedance.

In this article, we propose a simple and effective Z-input impedance method that augments the traditional TDR method for characterizing and optimizing via designs in much faster speed systems.