Recently, Signal Integrity Journal sat down with Dave Kohlmeier, the HyperLynx product line director of the Board System Division at Mentor, A Siemens Business, to talk about the latest engineering trends and challenges facing the industry. Below is a summary of our conversation (edited slightly for length).
Kohlmeier came to Mentor in 2002 through its acquisition of Innoveda, where he was leading the simulation and analysis business. Prior to that, he held senior engineering and marketing roles with a focus on new product development at Synario Design Automation, Data I/O and Tektronix. He has a B.S. in computer engineering from Rochester Institute of Technology.
SIJ: Within the competitive landscape of the industry, what are the greatest challenges your company faces technically?
Dave Kohlmeier: There are many challenges, but modeling data is probably the biggest. I remember a numerical equivalent that someone mentioned awhile back: “one picosecond is to a second as a second is to 31,000 years,” and we are trying to be picosecond accurate to verify these new interconnects. Well, to do that you need to be that accurate on all of the input parameters for your solvers. The solvers are just processing Maxwell’s equations, but they need input parameters that allow that level of accuracy.
For example: surface roughness affects loss, as does loss tangent; and stackup thicknesses have to be as-manufactured. Where are engineers going to get those parameters with sufficient accuracy? Estimates? Yes, but how many can cross-section a board? So our biggest challenge as an industry is working together to provide engineers with the modeling data they need. With the new standards like COM for channel margins removing the need for Tx and Rx models, it is on us to provide the super-accurate model of the channel.
SIJ: What about from a business perspective? E.g. international trade challenges, finding and keeping talent, reaching customers through new media? etc.
DK: I would say that finding talent and the “grey tsunami” are the industry’s biggest challenges. There is a lot of expertise ready to head out the door over the next decade, and EDA frankly isn’t as attractive as Amazon or Facebook for new engineers.
SIJ: Tell us about HyperLynx for SI/PI issue simulation, how did it come about, what was the evolution, and what technical or market challenges had to be overcome?
DK: This is a great story. Steve Kaufer and Kellee Crisafulli were working at Data I/O on a new project involving a bunch of signal-integrity work, and there wasn’t much in the way of tools on the market – and nothing on the Windows platform. So they did the late nights and weekends in the “basement” and started HyperLynx with the focus on easy-to-use PC-based software. Modeling was an issue then, as well. They were also founding members of IBIS along with Intel, Cadence, and a few others, to try and make it easier to get I/O Buffer models from the semiconductor industry.
SIJ: Can you talk a bit about your company structure? How do the different business units or teams interact in the product development/launch process?
DK: Well, as you know, Mentor is pretty much a software company. Our division (Board Systems Division) is 100% software. The sales organization runs across all divisions, so our job within the division is to define and create leading-edge software solutions for the creation and verification of electronic systems. HyperLynx is focused on verification, of course, but we work with other groups in the division to create integrated “platforms” like our flagship Xpedition Flow, with provides everything from schematic capture and layout, to power-integrity and manufacturing and shop-floor software.
SIJ: How do you foster innovation?
DK: Hire smart people and give them time and encouragement to create the next solutions. Giving them access to teaching customers is critical too. As I mentioned before, we don’t build any hardware so we need to stay pretty close to our customers to understand their upcoming problems.
SIJ: Your company does a significant amount of customer training in different formats (in person, online, etc.). How has that evolved over the years? What are you finding is becoming the more popular choice for your customers?
DK: Over the years, we started with instructor-led classroom training. This then has evolved to instructor-led dedicated private classes held at the customer’s site. Then, virtual delivery became common for global customers who could not travel, so instructor-led classes are now delivered globally by tools like WebEx. This allows multiple locations to attend.
Within the last few years, folks now want focused on-demand e-Learning, as the new generation of engineers learn differently today. For example, they want to watch a short video on how to do a certain task. This “Moment of Intent Learning” is now a standard way of learning and delivery, with short 5-7 minute videos on certain tasks that are searchable. They learn “what” they need “when” they need it. Also, hands-on labs add to the learning environment. Then, students take advanced instructor-led training, a blended approach to learning.
SIJ: What are the most common SI/PI applications questions that you are hearing from your customers?
DK: Most of our customer questions hit one of three main areas: SERDES, DDRx, and power delivery (both AC and DC).
For SERDES, it’s trying to verify that a channel will be “compliant” – in other words, that it meets the performance requirements set forth by the specification. Even though SERDES channels operate in relatively the same manner, the electrical requirements for each can vary widely from spec to spec. Similarly, DDR3 and DDR4 busses (and their other variants) have a number of complicated electrical and timing relationships that must be verified. Our reports are very comprehensive, but users have lots of questions regarding what actions or modifications to take to ensure that their interconnect meet the required specs.
The other issue that comes along with fast single-ended DDRx busses is the heavy impact the power distribution network, or PDN, can have on results. Customers are constantly trying to determine if they have the right board stackup and capacitors to meet their power needs because they can have a large impact on both cost and performance. So now they are performing more decoupling and DC drop analysis, and even taking that a step further by conducting a mixed SI/PI analysis to ensure that the effects of their PDN on their signals still leave them with enough margin.
SIJ: Can you share your product roadmap for SI/PI related products?
DK: I can’t be too specific, but I can tell you that above all, we are trying to make it easier for electrical engineers to perform these very difficult signal and power integrity issues. If you assume a shortage of SI and PI experts, then the key to success will be getting the hardware engineer to solve all but the toughest problems.
We need to help them make this transition from impedance focus to a loss focus. I may have mentioned this before, but I have used TurboTax as an example of a product that takes something very complicated (the American tax code) and reduces it to an interview, asking the questions that are sufficient to get a correct answer. We are trying to do that same thing. We have experts, so if we can embed our expertise into the product and walk the hardware engineer through the process to the solution, then we will be successful. The other focus is that we are more “protocol-centric” than before. Systems are large ICs tied together with a multitude of standard interfaces like PCI Express and DDR4. Focusing on verifying those interfaces for our customers is a more complete solution than just providing a simulator and field solver.