During DesignCon 2025, I had a number of side discussions with several people. The discussions involved my my DesignCon 2024 paper on dielectric anisotropy,¹ and how measured via test results they were measuring were not correlating well with the simulations when out-of-plane dielectric constant (Dkz) was converted to in-plane Dkxy using my heuristic method. From my paper, Isola’s Tachyon 100G, material anisotropy averaged in the range of approximately 4% to 6% over different glass styles, while others claimed an anisotropy of 10% to 12% was required for accurate simulation correlation to measurement. 

What’s going on? Well, there could be several reasons. 

The Short Answer

The anisotropy of glass reinforced laminates results in dielectric properties being different along the x, y, or z axis depending on the direction of electric field in the structure. Specifically, Dkxy refers to the case where the electric fields are parallel to the fiberglass cloth, while Dkz corresponds to the scenario where the electric fields are perpendicular to it. Determining material anisotropy is heavily dependent on the test fixture used to extract the properties.

In my paper,¹ I defined percent anisotropy (Λ) as:

(1) 

Attempts have been made to extract dielectric anisotropy based on a quarter-wave resonant structure^5,7 using a via acting as a stub. In principle, this is a good idea. A quarter-wave resonant structure causes nulls in the S21 insertion loss (IL) plots as shown in Figure 1. The first resonant null at 13 GHz is the fundamental frequency (f₀) and nulls at every odd-harmonic thereafter. Given the speed of light (c₀), the length of the stub and the effective dielectric constant (Dkeff), surrounding the via hole structure, the resonant frequency can be predicted by:

(2) 

If Dk is simply adjust in the 3-D field solver to fit the measured results base on an as-fabricated printed circuit board (PCB) cross-section (x-section) dimensions and use it to calculate anisotropy from Equation 1, it is really only providing an effective anisotropy (Λeff) to use in the model of a similar as fabricated via structure using the same dielectric material. It does not represent the bulk material anisotropy. 

Figure 1. S21 Insertion loss plot showing resonant nulls due to quarter-wave stub resonances.

As will be shown in this article, material anisotropy is not solely responsible for contributing to Dkeff surrounding a via hole structure. The as-fabricated drilled hole size and resin content of the actual pressed thicknesses must also be considered before applying my heuristic method to calculate Dkxy.

Finally, just as foil roughness affects Dkeff and phase or time delay (TD) in traditional PCB transmission lines, via barrel roughness influences the Dkeff surrounding it and increases TD. Since quarter-wave stub resonance is used to determine Λeff, an increase in Dkeff and TD lowers the resonant frequency, resulting in the perception of a higher anisotropy percentage.

The Long Answer

Since Dkeff defined as the ratio of the actual dielectric structure’s capacitance to the capacitance when the dielectric structure is replaced by air, Dkeff is directly proportional to capacitance. Furthermore, capacitance is also influenced by the electric potentials of surrounding metal structures. All 3-D field solvers account for this, so the only variation lies in what value of Dkeff is required for the model.

When modeling a via structure, we envision it as resembling the cross-section (x-section) illustration in Figure 2. In this example, the via barrels are perfectly smooth along their entire length. The antipads on each layer are aligned and symmetrical throughout the thickness of the PCB. The via barrel is surrounded by dielectric, and Dkeff is determined by the capacitance of the geometry. Many signal integrity (SI) engineers overlook the fact that all glass-reinforced laminates are anisotropic and instead they just use the bulk Dk value provided in laminate suppliers’ Dk/Df construction tables. They also assume that the final pressed thicknesses of the dielectric layers match the dimensions in the original as designed stackup drawing, and that the drill size specified in the computer-aided design (CAD) database corresponds to the actual size of the drill bit.

Figure 2. Cross-section illustration example of an ideal via structure.

But when we view an as fabricated x-section of a real via, we observe a different picture, as illustrated in Figure 3. In reality, the antipads are not always perfectly aligned layer to layer due to manufacturing tolerances. The via barrels  are rough and often feature random whiskers protruding into the dielectric along its length. Since the via passes through a mixture of resin and fiberglass cloth, we need to use Dkxy value, which may differ from the bulk Dk published in the Dk/Df construction tables.  The actual pressed thickness of the dielectric layers, measured from the x-section sample, can be different than the stackup drawing values used in the model. Furthermore, most CAD software specify the drill as finished hole size (FHS), not the actual drill diameter, which is the outer diameter of the via barrel. All these anomalies will affect Dkeff surrounding the via hole structure.

Figure 3. Cross-section illustration example of typical via structure as fabricated.

Via Capacitance

In a true coaxial structure, as illustrated in Figure 4, the electromagnetic (EM) fields are completely contained within an outer ground (GND) shield that encloses a central conductor, separated by an insulating dielectric material. The electric field (E-field) determines capacitance and magnetic circular H-field determines the distributed via  inductance. The mode of wave propagation is referred to as transverse electromagnetic mode (TEM). 

Figure 4. Anatomy of a coaxial transmission line geometry and the electromagnetic field patterns with respect to TEM wave propagation through the structure.

A closer look at the anatomy of the via structure is illustrated in Figure 3. Although it resembles a coaxial structure, the via is surrounded by anti-pad clearance holes in the ground (GND) reference planes, along with multiple GND vias, rather than a continuous shield. The GND vias localize the EM fields in the dielectric cavity between reference plane layers but they do not perfectly contain them, resulting in quasi-TEM wave propagation.

In Figure 5 Section A-A, the electric field determines capacitance and are represented as distributed via capacitance (Cvia). Magnetic circular H-field determines the distributed via inductance (Lvia).  For a multi-layer PCB structure with several GND reference planes distributed evenly throughout the thickness, as illustrated in Figure 5, the via capacitance is mainly influenced by the drill size (Drillϕ), antipad diameter (Antipadϕ), and/ to some extent/ any GND vias in close proximity. 

Figure 5. Anatomy of a single via structure surrounded by GND reference vias.

Thus, the via capacitance can be approximated using Equation 3. Increasing the drill diameter or decreasing the antipad diameter results in a higher capacitance, since the space between the outer diameter of the via barrel and the diameter of the antipad becomes smaller.

(3) 

where:

Cvia = capacitance of via in F/per unit length

ε₀ = permittivity of free space = 8.854 pF/m or 0.225 pF/inch

Dkxy = in-plane dielectric constant

Antipadϕ = antipad diameter

Drillϕ = drill diameter

CAD software defines FHS in the PCB layout. To add to the confusion, some CAD software also call this drill size. Fabrication notes will specify actual drill diameter tolerances and the board shop will adjust these to meet plating hole thickness depending on PCB class the design has to meet. The actual drill diameter is at least 2 mils larger than the FHS but may be 3-4 mils larger depending on the plating requirements specified. When engineering design automation (EDA) tools import the design database for SI analysis, it is the FHS that gets imported. This is a common trap SI engineers fall into when modeling vias, and using the FHS instead of actual drill size will under estimate via capacitance and thus Dkeff.

Non-functional (NF) pads (not shown) are pads attached to the via on layers that serve no function. In other words, they do not connect to any traces. Years ago, they were included because it was thought they improved via mechanical reliability and had little effect on the signal integrity of the time. Including non-functional pads will decrease the space between the pad's outer diameter and the diameter of the antipad, thus increasing capacitance, unless the antipads are enlarged to compensate. Today, milti-gigabit designs specify non-functional pads to be removed to mitigate excess capacitance. Ideally this is done in the original artwork, but sometimes it is left to the PCB fabricator to remove them before fabricating.  If the fabrication notes are poorly communicated, then you could end up with NF pads resulting in poor SI correlation to measurements. Unless you do a micro-section, you will not know and draw the wrong conclusions. 

Via Roughness

Roughness of the via barrel is mainly caused by copper platting wicking into voids in the drilled hole caused by drill bit crazing the glass reinforcement weave, and is usually caused by a dull drill bit. It is usually not considered when modeling a via, but is a factor when trying to do SI correlation. 

Figure 6 is an illustration showing a blowup of copper plating wicking into the glass bundles. IPC-600G⁴ defines acceptable amount of wicking allowed depending on the class the PCB has to meet. It can be as high as 125 µm (4.291 mils) for Class 1 to as low as 80 µm (3.15 mils) for Class 3.

Figure 6. Copper plating wicking into glass crazing caused by drill bit.

Via barrel conductor roughness has the same effect on increasing via capacitance resulting in higher Dkeff in the same way copper surface roughness increases self-capacitance (C11) of transmission line geometries.² Since wicking extends past the actual drill diameter it concentrates the electric fields and increases capacitance. 

This is validated by HFSS simulations, as shown in Figure 7. Figure 7(A) and Figure 7(B) show color maps of E-field strength in cross-section for perfectly smooth and rough vias, respectively. As seen in the images, the E-field is primarily contained within the anti-pad opening of the reference planes, similar to its behavior in a perfect coaxial geometry. In this example, we observe increased E-field strength along the roughness profile in Figure 7(B), leading to a 2.6% increase in capacitance.         

Figure 7. Electric field strength color map and capacitance of smooth vias (A) and rough vias (B). Simulations courtesy of Juliano Mologni, Ansys. 

Unfortunately, achieving model correlation with via measurements is challenging due to the randomness of wicking and the via’s passage through the mixture of glass and resin. A single cross-section is insufficient because it represents only one slice of a 360-degree hole where wicking can be random anywhere around the circumference. For example, Figure 8 is a microscopic top-down view of a slice of an actual plated through hole showing copper wicking into the glass weave faintly visible running horizontal and vertical in the picture. By inspection we imagine slicing the via horizontally exactly at the maximum diameter would not have captured the maxim amount of wicking. It’s is also hard to measure exact via diameter after cross-sectioning because there is no guarantee the microsection was accurately cut at the maximum diameter. Depending on how square and accurate the cutting and polishing was, there can be slight variations in diameter.

Dkeff Compensation Due to Conductor Roughness

As shown in Figure 8, the measured inner ring diameter of 14.4 mils (365.8 µm) represents the FHS. The middle ring drill diameter is 18.43 mils (468.1 µm). By inspection, the outer ring diameter of 18.80 mils (477.50 µm) represents the drill diameter plus the average roughness. It should be noted that, because a via is round, it is analogous to a flat sheet of foil wrapped into a circle. Therefore, the actual surface conductor roughness is half the difference between the drill diameter and the average roughness diameter. In this case, the average surface roughness is calculated as 0.5 × (18.80 - 18.43), which is approximately 0.2 mils (5 µm).

Figure 8. Microscopic top-down view of a slice of an actual plated through hole showing copper wicking into the glass weave faintly visible running horizontally and vertically.

Heuristically, we can estimate additional capacitance and Dkeff correction due to roughness for via example in Figure 8. If the ratio of Dkeff_rough to Dkeff_smooth is defined as:

(4) 

From Figure 8, if Drillϕsmooth = 18.43 mils;  Drillϕrough = 18.80 mils and assuming a typical antipad diameter of 40 mils,   then by combining Equation 3, with  Equation 4, Dkeff_rough can be expressed by Equation 5. When plugging in the numbers, we see Dkeff_smooth increases by 2.6% as compared to Dkeff_smooth.

(5)

Via stub test vehicles are commonly used for SI model validation.^5,7 Via stubs are quarter-wave resonant structures that depend on TD, determined by the stub length, which is equivalent to one quarter of the period (T) of the resonant frequency. The common practice to extract Dkeff from the first quarter-wave resonant frequency null from an S21 IL plot similar to Figure 1 is:

(6)

But Equation 6 assumes that Dkeff is entirely determined by capacitance. However, for time-variant electromagnetic fields, inductance also contributes to time delay (TD). Via barrel roughness affects the self-inductance (L11) in the same way that copper surface roughness increases L11 in transmission line geometries. In my previous paper,³ Dkeff for time-variant electromagnetic fields is expressed as:

(7) 

where: c₀ = speed of light; L11 = Self-inductance; C11 = Self-capacitance.

Equation 7 clearly demonstrates that an increase in L11 leads to a proportional increase in Dkeff. Failure to use software that incorporates a causal metal roughness model, such as the Bracken model [8], to account for inductance caused by conductor roughness can result in misinterpreting the extracted Dkeff value and misunderstanding the impact of anisotropy.

To validate my hypothesis, I reached out to my friend, Juliano Mologni from Ansys for some help with an experiment to add roughness to a via ¼ wave stub structure. The goal was to see if we can observe any measurable change in resonant stub frequency and thereby quantify its effect on extracted Dkeff using Equation 6. 

He created a simple six layer via stub structure in HFSS, as shown in Figure 9. The drill diameter was 10 mils (254 um), antipad diameter was 50 mils (1.27 mm) and six stitching vias equally spaced at 60 mils (1.52 mm) diameter as shown. The port 1 – port 2 feed traces were on the top layer to achieve a maximum via stub length of 150 mils (3.81 mm). Dielectric Dk was 3.97.

We used the Huray roughness model, incorporating the causal Bracken model, to account for added inductance due to conductor roughness. The Huray nodule radius (NR) was parameterized from 0 to 2 µm (78.7 µin) in 0.1 µm (3.94 µin) increments. Based on my Simonovich Cannonball roughness model,⁹ which stacks 14 spheres, the Hall-Huray surface ratio (SR) parameter remains constant at 4.9. Converting NR to Rz roughness is straightforward and simply calculated as: 

(8)

Figure 9. HFSS via stub model showing roughness added to all vias. HFSS simulation model courtesy of Juliano Mologni, Ansys.

Figure 10 plots the S21 IL showing the quarter-wave stub resonant nulls for 0-2 µm Huray NR roughness parameters. The resonant frequency was measured for each NR parameter and converted to Dkeff using Equation 6. Equivalent Rz was also calculated using Equation 8. This would translate to 0-33 µm Rz equivalent roughness.  

Since the Bracken model only corrects the imaginary part of the complex impedance of the rough metal, it does not correct the capacitance, so the increased Dkeff change is solely due to increased L11.  

Figure 10. S21 IL showing the quarter-wave stub resonant nulls for 0-2 µm Huray nodule radius (NR) roughness parameters. Simulation courtesy of Juliano Mologni, Ansys.

Figure 11 summarizes the simulated results in the table and the graph plots Dkeff vs. Rz roughness columns. By observing the third-order polynomial fit, we observe an exponential change in Dkeff and levels off at 4.03. This was surprising observation and further investigation to explain why it levels off was not done. None the less, the simulation results confirm our hypothesis and a Rz roughness of 10 µm seems reasonable average via barrel surface roughness.

Figure 11. Summary of extracted simulated results and graph plotting Dkeff vs. Rz via conductor roughness.

Dkeff Due to Pressed Thickness

The Dkeff of individual cores and prepreg layers within the finished PCB varies based on their final pressed thickness. The actual core and prepreg thicknesses must be precisely measured from micro-sections of the tested board for accurate simulation correlation. Since stackups are typically designed using the published Dk/Df construction table values, these values differ from the actual pressed thickness after board fabrication. During the pressing process, under heat and pressure, the dielectric loses resin content. Because the published Dk is based on a specific resin content prior to pressing, the resin loss in the pressed dielectric results in an increase in Dk.

Figure 12 shows the relationship between bulk Dk and thickness for Tachyon 100G 1078 glass style. Since a change in thickness corresponds to a change in resin volume, a linear fit equation can be used to adjust Dk based on pressed thickness. Consequently, the respective Dk values must be adjusted accordingly before converting from Dkz to Dkxy.

Figure 12. Linear fit of Dk vs. prepreg thickness for published values of Tachyon 100G 1078 glass style. 

Previous Study

In the DesignCon 2015 paper,⁵ the authors attempted to show that by using anisotropic dielectric models the modeling/simulation/measurement loop can be closed with simulation models of single-ended and differential vias. A simple test vehicle design was used to try and identify z-axis dielectric properties. 

Test Vehicle

A picture of the test vehicle and stackup, taken from the paper,⁵ are shown in Figure 13. The 12-layer PCB was fabricated with Tachyon 100G material. 

Figure 13. Test vehicle PCB and stackup reference DesignCon 2015 paper.⁵

Test Vehicle Model

The test vehicle HFSS simulation model is shown in Figure 14. A single microstrip trace, routed on the top layer, feeds a single via in the middle, creating a quarter-wave resonant structure. The via is surrounded by ground vias to localize the EM fields, approximating a coaxial structure as described earlier.

Figure 14. Simulation model used for analysis reference DesignCon 2015 paper.⁵

Anisotropy Test Vehicle Tachyon Results

Unfortunately, final measurement and simulation results were unavailable by the time of the proceedings publication. To gather more data from this study, I reached out to my friend Scott McMorrow, who graciously shared additional as fabricated and simulation information.⁶

Two via stub test structures, identified as Stub_1 and Stub_4,  of the same design located at different locations on the same test vehicle panel were x-sectioned for analysis. Using measured parameters for both via lengths and the Dk values from the as-designed stackup, a difference in stub resonance frequency of 1.054% for Stub_1 and 1.057% for Stub_4 was observed. This difference corresponded to an as-fabricated effective anisotropy (Λeff) of 11% and 12%, respectively, based on empirical measurements.