Power Integrity

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Dialog Semiconductor plc, announced that Dialog will become Telechips’ preferred power management partner for their Dolphin+QD (TCC8059), Dolphin 3E (TCC8053) / Dolphin 3M (TCC8050) and Dolphin 3H (TCC8060) platforms.

Engineers who design and model power distribution networks require accurate component level models from high frequency down to DC.  Accurate modelling of power connectors can guarantee best power transfer and minimize power-induced noise.  In this paper, which won a DesignCon 2020 Best Paper Award, the authors analyze the frequency-dependent resistance and inductance of various power connectors as well as pin patterns.

When is it appropriate to have a continuous plane, split planes, or no planes under an RJ45 connector? This article from Zachariah Peterson takes a closer look.

This simple measurement demonstrates the most important principle in SI/PI and EMI: that the return current will flow in the path of lowest resistance below about 10 kHz. But above about 10 kHz, the return current will begin to redistribute in the return path to be adjacent to the signal conductor. Read on to learn more.

The principles underlying SI, PI, and EMC are not magic, and they are not about mysterious energy flows in the space between conductors. They are firmly rooted in the fundamental properties of electromagnetic fields, with a 160 year long rich history. Embrace it!

Richardson RFPD, Inc., announced the availability and full design support capabilities for the Power by Linear Silent Switchers from Analog Devices, Inc.

In the high-speed connector design arena, there are two opposing ideas. For some people, if you simply put pieces of plastic and metal together, eventually you have a signal transmission. This process is very simple. On the other end of the spectrum, there is the idea that a solid connector design requires a deep understanding of electromagnetic theory, a wisdom only sorcerers and wizards possess.

As DDR data transmission rates continue to increase, the signal integrity of the DDR channel has become one of the most critical concerns. This article takes an extensive look at the impact of via stubs on the impedance of the signal lines on DDR4 memory, including test cases and ways to optimize design.

It takes only one rogue voltage wave to kill a PDN in high-speed digital designs. Flat impedance optimization before layout lowers the risk of rogue waves occurring in your design. Heidi Barnes explains how rogue waves occur and addresses how to get the best performance at the lowest cost.

We care about maintaining the same differential impedance for the same reason we care about maintaining the same instantaneous impedance of a single-ended (SE) transmission line: to avoid reflections. SIJ’s EAB member Bert Simonovich explains the fundamentals and why it matters.