Power Integrity

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Infineon Technologies AG has opened a new laboratory for the development of quantum electronics in Oberhaching near Munich.

In the process of circuit design, electrical engineers must carefully position capacitors to decouple the power supply pins of integrated circuits (ICs). Yet, relying solely on a single capacitor for this purpose may potentially decrease the performance of the Power Delivery Network (PDN). Therefore, there exists a need for an elegant and systematic methodology in designing the PDN while utilizing a single capacitor. Within this paper, we analyze the single-capacitor scenario within the context of the PDN and introduce a systematic approach for its design. This approach not only suggests clear guidelines for when favoring a single capacitor over multiple capacitors is appropriate but also showcases that when these guidelines are exceeded, this method can be implemented recursively to achieve an optimal PDN solution.

Automotive applications present new challenges to high-speed serial technology. Asymmetric, multi-gigabit signaling between sensors, processors, and displays in the unique noise environments of both electric and internal combustion engine vehicles create new problems for signal and power integrity engineers. This paper introduces the signal impairments required for receiver testing in the emerging automotive standards like ASA, MIPI's A-PHY, Automotive Ethernet, and more. Standards specify different sources of noise in different ways, some in the form of time evolutions, others as spectra. This paper focuses on techniques for generating and calibrating each noise source while describing advanced de-embedding techniques and addressing test equipment limitations.

Saelig Company, Inc. has announced the availability of the Pulsiv PSV-AD-250-DS Evaluation Boards for the OSMIUM Microcontroller family, which enables rapid customer evaluation of the ultra-efficient Pulsiv power supply technology. 

This paper investigates via and trace coupling effects using measurements, hybrid, and full-wave solvers by de-embedding/calibration utilizing multiple test-boards.

Renesas Electronics Corporation has announced a complete space-ready reference design for the AMD Versal adaptive system-on-chip XQRVC1902.

The Xpeedic EDA 2023 Suite includes 2.5D and 3D signal integrity and power integrity simulation for advanced packaging, along with three platforms to support 3D EM simulation, multi-domain co-simulation, and high-speed system simulation.

Inductance and resistance are fundamental to the design and analysis of Power Delivery Networks (PDNs). Excessive inductance and resistance can cause several severe power and signal integrity problems, as well as design failure. As we have seen, inductance can certainly be a confusing parameter. The type of the extracted resistance and inductance (loop or partial) depends on how the ports are connected to the model in the simulation. Consequently, their connection in the electrical circuit and the level of voltage details we can get from the simulation results will be determined. In many cases, it is required to know the voltage drop on the PWR path and on the GND path separately, therefore it is necessary to use partial inductances and resistances. The method of expressing SLI with partial inductances and the ideas behind it are briefly described in this paper.

Patented set of technologies unleashes GaN to operate at up to 20 MHz for the first time without overheating or RF issues, opening up a vast new application area for GaN.

In this article covering next-generation USB technology, Keysight reviews IP/PHY development kits, simulation solutions, and T&M solutions that serve as the foundation for silicon and system integrators to design compliant USB4 Version 2.0 products that meet strict interoperability requirements in the vast Type-C ecosystem.