Signal Integrity

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200+ Gbps Ethernet Forward Error Correction (FEC) Analysis

DesignCon 2024 Best Paper Award Winner

In order to study what is needed and what has been adopted for the next Ethernet speed node of 200 Gbps per lane, this DesignCon 2024 paper, a recipient of the Best Paper Award, investigates different FEC schemes such as end-end, concatenated, and segmented FECs, examining how these different FEC schemes affect signal integrity and performance in different end applications. 


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Ethernet in the Age of AI

In this blog, John D'Ambrosia discusses the industry's approach to Ethernet in the age of AI, from the IEEE P802.3dj project to the efforts of the Ultra Ethernet Consortium to deliver a complete cost-effective Ethernet architecture optimized and scalable for high-performance AI. Read on to understand the role of these two complementary efforts to support AI workloads and gain insight into potential industry growth.


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