Anil Pandey is currently a Principal R&D Engineer at Keysight Technologies. Before joining Agilent (now Keysight) he worked 4 years as Scientist in Indian Space research organization (ISRO). He received his Bachelor of Engineering (ECE) in 2001 from Kumaon University, Nainital, and Master of Technology (Microwave Engineering) from Indian Institute of Technology (IIT-BHU), Varanasi in 2003. He has experience in RF, Microwave, Signal Integrity and Power Integrity analysis for high speed systems and Antenna Design. His areas of interest are signal integrity, power integrity, EMI/EMC, RF/Microwave circuits and Antenna designs. Anil Pandey has served as a reviewer for many international journals, such as IET, ACES, EDI Con and Antenna Journal. He has delivered invited talks in various conferences and institutions including IIT Jodhpur, SSPL Delhi etc. He has more than 35 international and Nation research publications to his credit. Apart from academics, his hobbies are creative writing and reading books.
The increased data rates of today’s high-speed Input/Output (I/O) buses make maintaining transmission channel signal quality all the more challenging. One reason for the challenge is the parasitic effects that result from bus interconnects. Over the past decade, data rates for electrical interconnects have experienced a dramatic increase—from 1 Gbps to 25 Gbps and beyond—to meet the ever increasing demand for more I/O bandwidth from modern networking applications and high-capacity storage.