Items Tagged with 'PCB'

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Plated-Through-Hole Via Design Specifications for 112G Serial Links

Recent studies indicate that the industry is nearing the precipice where plated through hole via technology has reached a limit in supporting serial links with 28 GHz Nyquist frequency requirements. At DesignCon2021, a team from the Mayo Clinic presented this paper about their work to extend the “life” of conventional PCB technology.


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Utilizing Fine Line PCBs with High Density BGAs

With the recent introduction of the Averatek Semi-Additive Process (A-SAP) process, linewidths under 1 mil are possible using the same fabrication processing line as for traditional 4 mil wide lines. This opens up the possibility of using narrower traces in the BGA escape region than in long-path routing regions. However, using this routing architecture means the narrower traces in the BGA escape field are at a higher impedance than the wider, 50 ohm traces in the routing region. So, how long can these traces be before the impedance mismatch is a problem? The authors of this piece propose an analysis methodology to find out.


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Validation of Bend Models with Measurements

Bends in PCB traces look like very basic, simple structures that are easy to simulate. Technically, one can do the analysis with any electromagnetic solver with sufficiently accurate port de-embedding capabilities. The reflections from a bend in fine-line, high-speed digital interconnects are relatively small and may not even be detectable with measurement. So, who cares? Read on to find out more.


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Stackup Beware: Case Study of the Effects on Transmission Line Losses Due to Mixed Reference Plane Roughness

Designing the right PCB stackup can make or break product performance. If the product has circuitry that is impedance and transmission loss sensitive, then paying attention to conductor surface roughness is paramount. Sometimes, however, the roughness of adjacent reference plane(s) is overlooked. If the adjacent high-speed signal layer uses smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur and possibly cause a product to fail compliance. So, how is this determined before finalizing the stackup? Read on to find out.


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112 Gbps PAM4 Silicon and Connector Evaluation Platform

The continued progression to higher data rates puts increasing demands on the design of practical SerDes channels. At 112G-PAM4, the UI is only 17.86 ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk, and power integrity. This article summarizes the key elements of a study that describes the signal-integrity and power-integrity design process and shows simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors. 


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