Items Tagged with 'Inductance'

By treating the resistor as an electromagnetic structure rather than a lumped element, and by managing coupling, shielding, thermal paths, and compensation as part of a unified design, it becomes possible to achieve ultra‑low insertion inductance and gigahertz‑class measurement bandwidth in a device small enough for production use. The result is a measurement element that enhances system performance rather than limiting it. As power systems continue to push toward higher speed, higher density, and higher reliability, the current‑sense resistor must evolve accordingly. In this article, Steve Sandler outlines a path to that evolution.

This article covers the importance of proper calibration, measurement, and de-embedding to ensure that the final capacitor model is free of errors, allowing an accurate representation of the PDN used in simulation. While capacitor models may play a seemingly minor role in the overall system design, the impact of capacitor models can significantly impact the system design and, importantly, design sign-off.

Inductance and resistance are fundamental to the design and analysis of Power Delivery Networks (PDNs). Excessive inductance and resistance can cause several severe power and signal integrity problems, as well as design failure. As we have seen, inductance can certainly be a confusing parameter. The type of the extracted resistance and inductance (loop or partial) depends on how the ports are connected to the model in the simulation. Consequently, their connection in the electrical circuit and the level of voltage details we can get from the simulation results will be determined. In many cases, it is required to know the voltage drop on the PWR path and on the GND path separately, therefore it is necessary to use partial inductances and resistances. The method of expressing SLI with partial inductances and the ideas behind it are briefly described in this paper.

Steve Sandler was recently asked to measure a 25 mH inductor. Read on to find out what happened next.

SIJ technical editor Eric Bogatin notes that there are some problems that occur over and over again across product families and applications. They have a handful of essential principles at their underlying root cause. In this blog, he explains that if we really understand these underlying principles, the root cause of the problems will be more apparent and their solutions closer to implement.

Poor control loop stability results in degraded power supply rejection ratio, transient response, output noise, and, for mixed signal circuits, degraded jitter. Datasheet application examples and reference designs do not often include stability information, and measurements often conclude the stability is poor.

This article lays out the basics of signal integrity problems, explains s-parameters, and identifies challenges in high-speed design.