Items Tagged with 'FEC'

Industry leaders join forces to meet the next generation needs of service providers, 
5G telecom, and fixed access operators.

Viavi Solutions Inc. will highlight new Ethernet testing solutions at OFC 2023 in San Diego.

Anritsu Company demonstrates solutions, technologies, and methodologies to verify high-speed communications designs during DesignCon 2023.

What are the optimal methods (and their resulting challenges) to achieve 224/212 Gb/s common electrical I/O (CEI) and Ethernet, the highest speed/data rate per lane electrical input/output (I/Os) and link systems? By way of understanding, we begin by investigating optimal pulse amplitude modulation (PAML) vs. channel characteristics at 224 Gb/s.

What are the test challenges brought on by PAM4? This article details what a BERT needs to do to meet the necessary signal analysis requirements.

Interested in performance analysis for 100+ Gb/s per lane PAM4 interfaces? This paper takes a detailed look at high-speed serial link error propagation models and different Ethernet coding schemes as part of FEC performance analysis for 100/200/400 GbE systems with 100+ Gb/s per lane PAM4 interfaces.

Looking into advanced error code correction? Many techniques involve forward error correction. But what exactly is that and how does it relate to your design? Cathy Liu spells it out in this article.

This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE,  DFE, and FEC equalization schemes for serial links at and above 112 Gbps.