Anritsu Company showcased solutions, technologies, and methodologies to accurately and efficiently verify high-speed communications designs during DesignCon 2023, January 31 – February 2, 2023 in Santa Clara, Calif. Chip, board, and systems design engineers learned of innovative testing approaches through demonstrations featuring vector network analyzers (VNAs) and bit error rate testers (BERTs), technical sessions, and panel discussions during one of the industry’s leading electronic design conferences.

At DesignCon 2023, Anritsu conducted product demonstrations on advanced testing approaches that address complex designs. Two test solutions shown include:

  • PCIe® 6.0 Rx Compliance Test
    • Anritsu demonstrated a single-instrument PCIe solution featuring its Signal Quality Analyzer-R MP1900A. The first solution to support the new PCIe 6.0 Base Spec. receiver test, the MP1900A assures the signal integrity of chip designs utilizing PCI 6.0. As shown in the demonstration, the all-in-one MP1900A simplifies the compliance test worst-case configuration while supporting accurate Rx Link Equalization (LEQ) evaluation.
  • Signal Integrity
    • To characterize high-speed interconnects, printed circuit boards (PCBs), backplanes, fixtures, packages, and probes up to 70 GHz, Anritsu displayed its VectorStar™ 4-port broadband VNA. VectorStar can conduct accurate and repeatable single-ended, balanced differential, and mixed-mode S-Parameter measurements. Its ability to profile impedance along a line using Time Domain Reflectometry (TDR) and simulate the eye diagram for a high-speed channel was featured. Network extraction for fixture de-embedding and electrical-to-optical (E/O) and optical-to-electrical (O/E) transfer function measurements will also be shown.

Hiroshi Goto, senior architect at Anritsu, participated in two technical sessions and a panel discussion on emerging high-speed technologies:

  • PCIe 6.0 Rx Test Requirements
    • Goto gave an overview on current requirements for PCIe 6.0 Rx calibration and testing. He covered LEQ testing, as well as PAM4 Bit Error Rate (BER), Symbol Error Rate (SER), and jitter tolerance testing. Forward Error Correction (FEC) and Flow Control Unit (FLIT) mode uncorrectable burst error analysis will also be covered.
  • USB4® Version 2.0 Tx and Rx Electrical Compliance
    • This technical session provided an update on USB4 Version 2.0 electrical validation and compliance testing, associated test tools, and challenges in meeting USB-IF test program timelines. New USB4 Version 2.0 CTS requirements, PAM3 analysis for validation and debug, automated SigTest compliance testing, and receiver calibration and testing were discussed.
  • FEC and Signal Integrity
    • Goto sat on a technical panel entitled The Case of the Closing Eyes: Bridging FEC to Signal Integrity. He participated in a group discussion on FEC and how it can be impacted by signal integrity challenges, as well as testing architectures to help bridge FEC and signal integrity.

Anritsu participated in three joint demonstrations with fellow industry leaders. Each demonstration highlighted integrated solutions that address specific high-speed signal integrity challenges.

  • Tektronix and Synopsys®
    • Anritsu participated in a PCIe 6.0 live demonstration with Tektronix, Inc. and Synopsys that will highlight automating PCIe 6.0 Base Tx/Rx testing at 64 GT/s. The demonstration will feature the Anritsu MP1900A BERT with the Tektronix DPO70000SX real-time oscilloscope and silicon-proven Synopsys PCI Express 6.0 IP DUT.
    • The two companies demonstrated 100 Gbps (53 Gbaud) BER test and PAM4 eye pattern analysis through low-loss, SN-MT connectivity from SENKO and the Anritsu BERTWave™ MP2110A and Network Master™ Pro MT1040A.
  • Granite River Labs (GRL)
    • Anritsu and GRL exhibited an automated solution for high-speed serial bus receiver tests, such as PCIe, USB, Thunderbolt, and DP. It features the MP1900A with GRL software to establish a fast and flexible test method.