Items Tagged with 'Interconnects'

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How Interconnects Work: Anatomy of Crosstalk

Crosstalk in PCB and packaging interconnects is arguably one of the most complicated phenomena that may cause signal degradation. Crosstalk effects can be treated statistically as a deterministic jitter with a bounded distribution, but the distribution is usually not known. A direct analysis of a worst-case crosstalk scenario may lead to a system overdesign. Neglecting it in design may cause a system failure that is difficult to find and fix later in a design process. Distortions caused by crosstalk cannot be corrected by signal conditioning techniques at a receiver side. It is very important to understand the sources of crosstalk, how to quantify it and how to mitigate it efficiently, as Yuriy Shlepnev demonstrates in this installation of the "How Interconnects Work" series.


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The Reports of Copper’s Death May Be Exaggerated

About 150 years ago the first stable transatlantic cable was laid and messages were sent between Ireland and Newfound­land over copper. The data rate on this cable was not even 1 bit/sec, it was 0.1 bit/sec. Concerns over the cable reliabil­ity and the slow data rate led some to believe copper was doomed as a communication media for these long cables.


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How Interconnects Work: Bandwidth for Modeling and Measurements

Modeling and measurement of digital serial interconnects is usually done in the frequency domain. That means that the minimal and maximal frequencies (or bandwidth) should be defined even before the analysis or measurement begins. This post introduces a simple and practical way to identify the bandwidth with a numerical analysis of defects in a single bit (SBR) or single symbol response (SSR).


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Use a 2D Field Solver to Accurately Predict Characteristic Impedance

The first goal in any high-speed board stack up design is to engineer interconnects with a target impedance, and the first step in this process is to use a 2D field solver to explore design space with a virtual prototype. Just how well can a field solver predict the impedance of traces on a real board? This article aims to answer this question.


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Coming Up: Easier Signal Integrity Simulation Setup with IBIS 7.0

There was a time when the signal integrity of connections between digital ICs could be nearly ensured by following one simple rule: don’t connect more than some maximum number of input pins to any single output pin. Often the fanout limit would be around 7. No models, no simulations. Everything we needed was in the thick books of vendor datasheets that filled our shelves, the tree-killing viral precursor to AOL installation CDs. Ah, those were the days!


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