Items Tagged with 'Power Integrity'

Modern ASIC-based systems can no longer be designed by rules of thumb when it comes to power integrity. In this DesignCon 2022 paper, Ben Dannan et al explain a workflow using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN.  

In this article, Eric Bogatin uses the issue of power integrity to illustrate why dialog between experts is crucial. 

As a closing gesture to the SI, PI, and EMC/EMI community, we want to leave all of you with a year-end holiday gift for your continued support.

Understanding a few simple power integrity (PI) fundamentals can go a long way towards increasing design margins when delivering power to high-speed digital loads. In this piece, Heidi Barnes provides some fundamental lessons on impedance.

It pains me to say this, but there is such a thing as turning the TDR up too high and it is also easy not to have enough. If there is a “too high,” and a “not high enough,” there must also be a “just‐right,” or Goldilocks, setting. Using measurements, and a smattering of math, the Goldilocks setting answers
will be clear. Read on to find out how.

The principles underlying SI, PI, and EMC are not magic, and they are not about mysterious energy flows in the space between conductors. They are firmly rooted in the fundamental properties of electromagnetic fields, with a 160 year long rich history. Embrace it!

As DDR data transmission rates continue to increase, the signal integrity of the DDR channel has become one of the most critical concerns. This article takes an extensive look at the impact of via stubs on the impedance of the signal lines on DDR4 memory, including test cases and ways to optimize design.

It takes only one rogue voltage wave to kill a PDN in high-speed digital designs. Flat impedance optimization before layout lowers the risk of rogue waves occurring in your design. Heidi Barnes explains how rogue waves occur and addresses how to get the best performance at the lowest cost.

Check out this description of what is likely the fastest GaN edge-speed ever recorded.

Automotive design has captured the public’s imagination, and their expectations are creating countless technical challenges for engineers working in this space. For SI/PI/EMC/EMI engineers, the challenges are unique inside the car due to harsh environments as well as crowded systems.