Items Tagged with 'noise'

Reducing various types of noise such as reflections, mode-conversion, return-path bounce, and crosstalk becomes a serious challenge in signal integrity designs of high data-rate interfaces. In this article, Dror Haviv focuses on the analysis and properties of the FEXT, presenting an alternative way to analyze the FEXT and its properties using the superposition theory of the differential signal and the common signal.

Automotive applications present new challenges to high-speed serial technology. Asymmetric, multi-gigabit signaling between sensors, processors, and displays in the unique noise environments of both electric and internal combustion engine vehicles create new problems for signal and power integrity engineers. This paper introduces the signal impairments required for receiver testing in the emerging automotive standards like ASA, MIPI's A-PHY, Automotive Ethernet, and more. Standards specify different sources of noise in different ways, some in the form of time evolutions, others as spectra. This paper focuses on techniques for generating and calibrating each noise source while describing advanced de-embedding techniques and addressing test equipment limitations.

In this power-electronics article, we focus on noise measurement of 48 V range voltage regulators (VRs), up to a maximum of 65 V. We propose a noise measurement setup and examine this method.

Do I really need to use a power rail probe to measure ripple and noise? Power rail probes are single ended, so does that mean I can only monitor one power rail at a time? Are there other, more affordable options available? In this blog post, Steve Sandler answers to these questions and more.

SIJ gets Dr. McMillan’s take on what matters for noise generation in SI/PI design, and how PAM4 is arriving.

This article examines the key noise processes involved in measurements of jitter and phase noise, shows how these processes impact test results for various types of test equipment, and provides insight for interpreting these results.

A common design technique for power distribution networks (PDN) is the determination of the peak distribution bus impedance that will assure that the voltage excursions on the power rail will be maintained within allowable limits, generally referred to as the target impedance. In theory, the allowable target impedance is determined by dividing the tolerable voltage excursion by the maximum change in load current.