Benjamin Dannan

This article covers the importance of proper calibration, measurement, and de-embedding to ensure that the final capacitor model is free of errors, allowing an accurate representation of the PDN used in simulation. While capacitor models may play a seemingly minor role in the overall system design, the impact of capacitor models can significantly impact the system design and, importantly, design sign-off.

In the final installment of this blog series, Benjamin Dannan, Heidi Barnes, and Steve Sandler continue their discussion of how to calculate the minimum CMRR with a PDN impedance measurement using a 2-port probe, demonstrating how to measure a sub-40 µΩ impedance when using an isolator that has sufficient CMRR using two different VNAs, the Bode 100 and E5061B. Achieving sub-40 µΩ impedance measurements is challenging, but completely realistic with the proper test equipment. 

Having determined the amount of CMRR needed for 2-port measurement in the previous installment of this blog, Steve Sandler and  Benjamin Dannan return with a demonstration of how to create a DUT and make a 40 µΩ impedance measurement with the 2-port probe.

As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all of your simulation models are correct. System designers typically assume that all of the vendor models are correct. So, what does an engineer do if one of the ASIC die models needed for a power integrity simulation is incorrect? 

In this blog, Steve Sandler and Benjamin Dannan demonstrate how to determine how much CMRR is needed when introducing a ground loop isolator to correct the error in a 2-port measurement. 

This paper addresses the challenge of how to simulate the power integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation.

Modern ASIC-based systems can no longer be designed by rules of thumb when it comes to power integrity. In this DesignCon 2022 paper, Ben Dannan et al explain a workflow using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN.  

This article shows the impact of using one of the first DDR4-3200 FPGA memory controllers, the Xilinx Versal, interfaced to a UDIMM to show a method for accurately correlating signal integrity simulations to measurement.

If you have designed a controlled impedance transmission line based on a PCB stack-up, how do you know if the PCB fabrication house or another vendor built your stack-up to meet your controlled impedance specification?