Articles by Steve Sandler

Designing Power for Sensitive Circuits

Low power, high performance circuits are often plagued by power supply related issues.  This common occurrence is frequently due to mythical (or misapplied) rules-of-thumb.  These rules of thumb often lead us in the wrong direction, making things worse rather than better.  In this article, I’ll highlight some of the most common mistakes engineers make and share some fundamental rules for designing clean power for sensitive circuits.  Applying these rules will result in higher performance, lower cost designs with fewer design iterations.

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Three stability assessment methods every engineer should know about

Many engineers are familiar with the Bode plot as an effective stability assessment method.  However, some authors suggest and even teach that the Bode plot is the only method needed.  This article shows why this thinking is short-sighted. A single, low cost instrument that can produce Bode plots, as well as two other stability assessment methods is discussed providing a more comprehensive stability assessment set of guidelines.

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PDN issues can occur in the simplest of circuits

When we think of PDN, the first images that usually come to mind are FPGA’s and CPU’s.  These circuit generally require ultra-low PDN impedance in order to maintain the appropriate voltage at the FPGA or CPU during the large dynamic current variations these devices present.

This study focuses on a much smaller scale addressing a very simple circuit comprised the related PDN issue.  While the issues shown here may seem obvious to some, this is an excellent example of what is a very common problem.

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Two Common Power Delivery Network Measurement Issues

There are many questions about measuring Power Delivery Networks (PDN), but these two are very common ones.  Why do we calibrate the 2-port measurement with a 1Ω shunt resistor and why do I use DC blockers on both ports?  In this article I’ll provide responses to both of these questions.  The measurement setup in Figure 1 is an example where I used both the 1Ω calibration and the inclusion of the DC blockers.

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Evaluation of Gallium Nitride HEMTs for VRM Designs

As systems designers work hard to squeeze more and more features into less board space, the power delivery paths are becoming increasingly complex. The current mature VRM designs based on Silicon MOSFETs are hardly meeting present day requirements. One of the promising technologies touted to solve this conundrum of space and performance constraints is GaN HEMT. However, many engineers are hesitant to design very high frequency GaN VRMs from the ground up. This paper evaluates the steps required to modify existing Si-MOSFET designs for use with eGaN HEMT devices. The paper also compares the expected performance of GaN vs. Si in linear and switching regulator topologies and covers some of the measurement challenges as well.

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