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Read on to see how to determine if you should you use a differential pair in your test coupon and pay for a 4-port measurement, or use a single-ended test line and only pay for a 2-port measurement.
DDR memory interfaces are becoming increasingly common, and present a unique set of challenges to those designing high-speed embedded systems. This article will examine what DDR interface testing is all about, concentrating primarily on the physical layer and solutions to common problems.
Levent Sevgi, who has worked with electromagnetics for almost three decades, wrote this book to address the breadth of EMC engineering topics that are not covered by more specialized texts: market control, accreditation, calibration, EMC testing and measurement and mitigation.
This is the first year that NIWeek has taken place in late May instead of its normal early August time slot and switches permanently to this part of the calendar. NIWeek 2017 kicked off with new CEO Alex Davern paying tribute to Dr. T with a standing ovation from the audience. Read this summary of what happened at NIWeek 2017.
Holey Swiss cheese offers a popular metaphor for describing planes with a high density of clearance holes, usually under a BGA escape. The concern of many designers is the impact on the inductance in the power and ground planes due to all those holes. Since the gaps between them is narrow, won’t they constrict the current, dramatically increasing the series resistance and the loop inductance of the planes?
If you’re looking for a handbook on SI characterization techniques, or more specifically, TDR and VNA measurements, check out the second edition of this popular book.
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