Power Integrity

TA_Designing Power for Sensitive Circuits

Designing Power for Sensitive Circuits

How do you design power for sensitive circuits including LNAs, clocks, and PLL circuits? Although these circuits consume low power, they are sensitive to even very low levels of power rail noise. This EDI CON USA 2017 Outstanind Paper Award wining paper discusses the various noise paths that contribute to the degradation of the sensitive circuit as well as how to optimize, measure, and troubleshoot power supply related noise for these applications.


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Flapping Switch

Current Sharing Measurements in Multi-Phase Switch Mode DC-DC Converters

This paper, presented at EDI CON USA 2017, demonstrates the use of a special probe tip utilized to convert a differential measurement of inductor voltage to a measurement of inductor current. It shows the connection and calibration considerations in the measurement of inductor current, including the digital signal processing algorithms required to compensate for the components in the power supply and the probe tip. It also explains current sharing measurements made in the time and frequency domain using a transient current generator.


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Measuring Sub-milliOhm PDN Impedance

Measuring sub-milliOhms is difficult.  Getting low noise, sub-milliOhm measurements in very small circuits is a bit more difficult.  We recently had the opportunity to support R&D Altanova in performing this difficult measurement, here are some of the results.


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Figure 4

Practical DDR Testing: Compliance, Validation and Debug

DDR memory interfaces are becoming increasingly common, and present a unique set of challenges to those designing high-speed embedded systems.  This article will examine what DDR interface testing is all about, concentrating primarily on the physical layer and solutions to common problems.
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