Jaclyn Seigal, SIJ Assistant Marketing Manager
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Signal Integrity / Power Integrity / EMC/EMI

Top 5 Articles of All Time

December 13, 2021

As rated by reader views, here are the Top 5, Most Read Articles on SIJ of all time. Thank you for your continued readership, as we look forward to bringing you many more great technical features in 2022 and beyond!

Article 1

The Myth of Three Capacitor Values

By Eric Bogatin, Larry Smith, and Steve Sandler

Many designs today include three different value decoupling capacitors, or when using just one capacitor, a small value like 0.1 uF. These recommendations are based on 50-year-old assumptions that do not apply today. It is time to reconsider these out of date, legacy design guidelines. Read on to see more.

Article 2

A Guide for Single-Ended to Mixed-Mode S-parameter Conversions

By Bert Simonovich

Signal integrity engineers almost always have to work with S-parameters. If you have not had to work with them yet, then chances are you will sometime in your career. As speed moves up in the double-digit GB/s regime, many industry standards are moving to serial link-based architectures and are using frequency domain compliance limits based on S-parameter measurements. Read on to see more.

Article 3

What is FEC, and How Do I Use It?

By Cathy Liu

Looking into advanced error code correction? Many techniques involve forward error correction. But what exactly is that and how does it relate to your design? Cathy Liu spells it out in this article. Read on to see more.

Article 5

Ensuring High Signal Quality in PCIe Gen3 Channels

By Anil Kumar Pandey

The increased data rates of today’s high-speed Input/Output (I/O) buses make maintaining transmission channel signal quality all the more challenging. One reason for the challenge is the parasitic effects that result from bus interconnects. Over the past decade, data rates for electrical interconnects have experienced a dramatic increase—from 1 Gbps to 25 Gbps and beyond. Read on to see more.

Article 2

S-parameters: Signal Integrity Analysis in the Blink of an Eye

By Alfred P. Neves and Mike Resso

Emerging 100 Gigabit Ethernet and 400 Gigabit Ethernet requirements for communication networks have put increasing demands on Internet infrastructure. New methods of design, validation, and troubleshooting to optimize high speed digital channels are being employed in the R&D laboratory. This article discusses new concepts for serial link design and analysis as applied to physical layer test and measurement techniques. Read on to see more.


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