Silicon Labs has expanded its timing portfolio to meet the high-performance clocking requirements of 56G PAM4 SerDes and emerging 112G serial applications. With this portfolio expansion, Silicon Labs offers a comprehensive selection of clock generators, jitter attenuating clocks, voltage-controlled crystal oscillators (VCXOs) and XOs for 100/200/400/600G designs that satisfy sub-100 fs reference clock jitter requirements with margin.