Eric Bogatin, Signal Integrity Journal Technical Editor
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Eric Bogatin is Technical Editor at Signal Integrity Journal and the Dean of the Teledyne LeCroy Signal Integrity Academy. Additionally, he is an Adjunct Professor at the University of Colorado - Boulder in the ECEE Dept. Eric improves the signal to noise ratio by sorting through all of the information available and finding the best quality content to publish on

Signal Integrity

State of the Art Laminates Still Have Some Life Left

September 20, 2018

I recently came across a video recording of a presentation by Terence Regan, a Field Application Engineer from Amphenol of a talk he gave at DGCon in Israel in 2017. As Terence says in his intro, he’s been in this field of high performance interconnect design and fabrication for more than 35 years, so has the street cred. I have found in life, when someone as experienced as he is offers to share his insights, it’s usually worth your time to listen. Here is some of what I learned.

Amphenol is in a unique position of being a fab shop building high performance, large area boards, and also supplying the connectors used in many of these backplane applications. This positions them to “see things a generation before they come to market,” he says. Figure 1 is an example of a 50 GBps NRZ backplane test system they fabricated.

Figure 1. 50 Gbps NRZ demonstration vehicle using a Paladin connector system.

They are in high volume production of 10-25 Gbps NRZ backplanes and are working on 56 Gbps NRZ and 112 Gbps PAM4 applications.  Interconnects on their backplanes are typically 24 to 32 inches long.  In this realm, everything matters.

Data sheets of material properties from fab vendors may be very accurate but only apply to the specific combination of laminate thickness, glass type and layers, core and pre-preg combination, thickness and processing for that specific measurement. Change any one of these, and the effective Dk and Df will change.

Amphenol builds SI test vehicles using every combination of laminate thicknesses, glass, core and pre-preg and copper foil treatment that they intend to use in a backplane to characterize the Dk and Df properties. With this database, Terence says they are able to get excellent predictions of the impedance and loss properties of any interconnects.

They have developed a new material/copper system they call UltraSpeed™  which, combined with Megtron 7 laminates, offers more than 6 dB lower insertion loss at 25 GHz than a standard process Megtron 6.

To achieve this lower loss requires a low loss laminate but also ultra-smooth copper and a bonding treatment that does not affect the roughness. Figure 2 shows a comparison of the various types of treated electro deposited copper and their laser-profilometry measured roughness. “Keep in mind there is a difference between the starting roughness and the as fabricated roughness. This is why performance measurements after fabrication is essential,” he says.

The Ultra Speed baseline is the smoothest copper of any.

Figure 2. Measured surface profilometry of various electrodeposited copper foils.

The downside, of course, is the poor adhesion to most laminates. The ultra-smooth foils are not recommended for outer layers.


Because many of their backplanes are large, they are also thick, some as thick as 400 mils with 24 to 60 layers. This means stub length control by back drilling is essential. In one backplane, there can be more than 100,000 back drilled vias, all in addition to the normal through hole vias in the board.

For 28 Gbps NRZ performance, the backdrilled vias are precision drilled to leave a residual stub of 4 +/- 2 mils worst case, from both sides. They developed their own proprietary technique to “electrically” determine how close to the “live” layer they drill and a closed loop sensing system. Figure 3 is an example of 4.2 mil residual stubs in backdrilled vias.

Figure 3. Back drilled vias to a precision of 4.2 mils from the live signal layer.

Impedance Control

Requirements are now to 5% accuracy. They do not have the option of sorting. They need to achieve this tolerance by materials characterization and process control, such as layer to layer registration, when the planes above and below are segmented.

Amphenol will typically run as many as 100 different laminate materials over a years worth of designs. They build test vehicles and measure the properties for each layer and copper foil combination that are used in a design. Often times, “the materials properties we measure are not even close to the materials datasheet, because the data sheet is for a specific combination of layer thickness, glass content and type and foil.”

“PCB technologies can absolutely support 56 NRZ signaling and beyond. It’s cost effective, its proven technology and it’s been with us a long time, and will continue to be. We have a lot of life left to support the electronics industry,” Regan concludes.

Where is the future?

Advancing interconnect options to the next higher data rate generation seems to get harder and harder. Amphenol has demonstrated that by doing everything right, and reducing copper losses, 56 Gbps NRZ is potentially possible. But, can we get much beyond 56 GBps, or will other approaches, such as cabled backplanes, PAM4 or optical backplanes be required?

I think it will be a matter of cost effectiveness. As the I/O drivers on more ASICs, FPGAs and processors incorporate PAM4 capabilities, we may find competition in the 56 Gbps space between the highest performance PCB technology running NRZ signals and just “advanced” PCB technology incorporating 14 GHz Nyquist signals running PAM4.

The right decision will be based on the same trade off equation we have used for the last 50 years of electronics: which approach offers acceptable performance at the lowest cost, risk and schedule? As Amphenol has demonstrated, PCB based options are still in the running for 56 Gbps. Will they be for the next generation at 112 Gbps?


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