Items Tagged with 'stackup'

ARTICLES

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Introducing an Upcoming IEEE Packaging Benchmark

In recent years, the IEEE Electrical Packaging Society technical committee for electrical design, modeling, and simulation recognized the need for open-source benchmarks for the simulation tool, verification, and test and measurement solution vendors. The intention is to overcome the obstacles that developers and users of such tools and instruments often encounter and create a growing library of benchmark cases for signal and power integrity challenges. As of October 2023, there are four published benchmark cases in the repository. This article describes a proposal for a fifth benchmark.


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The Importance of Owning the PCB Stackup Process

In this article, Kella Knack outlines the stackup process, highlighting the importance of taking material issues, structural issues, and performance factors into account from the beginning of the design process. Knack discusses how providing fabricators with proper design documentation that includes precise information enables them to build to specification, ensuring correct functionality while avoiding additional costs for design.


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Stackup Beware: Case Study of the Effects on Transmission Line Losses Due to Mixed Reference Plane Roughness

Designing the right PCB stackup can make or break product performance. If the product has circuitry that is impedance and transmission loss sensitive, then paying attention to conductor surface roughness is paramount. Sometimes, however, the roughness of adjacent reference plane(s) is overlooked. If the adjacent high-speed signal layer uses smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur and possibly cause a product to fail compliance. So, how is this determined before finalizing the stackup? Read on to find out.


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