Items Tagged with 'DDR5'

ARTICLES

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What to Expect in a Multi-Drop Bus

In earlier DDR systems, the clock, command, and address signals (here in referred to as C/A) were distributed to multiple DRAMs using a forked topology, in which these signals propagate to all the DRAMs in the system at approximately the same time. The propagation delays on the command and address lines (in such systems) introduced timing skew into the system, limiting the operating frequency of the bus and eventually impacting the performance of these memory systems.


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DDR5 Signal Integrity Fundamentals

The most notable difference between DDR5 and previous generations is the introduction of decision feedback equalization, a technique used in serial link systems to improve the integrity of received signals.  In the wake of the new technology, this short article outlines some of the fundamental signal integrity concepts in the context of DDR5.


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A Brave New World: Simulating DDR5

Eagerly anticipated, the next generation of DRAM technologies (DDR5/LPDDR5) are presently being validated in the lab by leading silicon vendors worldwide. This latest generation has a big surprise in store for hardware engineers and SI specialists that need to simulate such systems. DDR5 will introduce decision feedback equalization (DFE) for the DRAM receiver for the very first time.


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