Eagerly anticipated, the next generation of DRAM technologies (DDR5/LPDDR5) are presently being validated in the lab by leading silicon vendors worldwide. This latest generation has a big surprise in store for hardware engineers and SI specialists that need to simulate such systems. DDR5 will introduce decision feedback equalization (DFE) for the DRAM receiver for the very first time.

Until now, the standard simulation workhorse for memory system design has been a transient (SPICE) engine, specifically using IBIS models for the DDR IO buffers, or sometimes SPICE models in lieu of IBIS. The introduction of DFE has upset the status quo of the modeling ecosystem, and the last two years has seen much discussion in the EDA community, publicly within IBIS Open Forum, and behind closed doors with system designers and silicon vendors alike.

The crux of the problem is that we now expect DDR5 memory systems to operate with a near closed eye at the input to the DRAM. In order to quantify the design margin, the hardware engineer simulating their design needs to have control over the equalization (EQ) parameters on both the DRAM and the memory controller at the same time, to arrive at the final eye as seen by the receiver slicer. How the EQ is performed, and the special signal conditioning that the receiver may provide to both clock and data signals, is completely the intellectual property of the silicon vendor or PHY IP provider. These are model details that are closely guarded.


It may come as no surprise that several major silicon vendors and some PHY IP providers have looked to IBIS-AMI (algorithmic modeling interface) as a solution to this problem. IBIS-AMI is a mature simulation methodology that has been successfully adopted by the industry for simulating high-speed serial interfaces. IBIS-AMI is an extension to traditional IBIS analog models, whereby the digital logic such as EQ, clock, and data recovery circuitry, and adaptation of EQ modes or slicer thresholds, could be wrapped up as compiled models (.dll). This hides the implementation from the model user, yet exposes the desired parameters that are to be adjusted or swept during simulation. These IBIS-AMI models are most typically used in a reference simulation flow by a channel simulation engine. Channel simulation with IBIS-AMI models came to dominance to solve one important question: What will my system bit error rate (BER) be?

To an SI engineer, a single BER number is just part of the question; it is also equally important to know what are the optimal equalization settings that will give me the most margin, and just exactly how much voltage and timing margin remains at my desired BER? This last item is tricky, because often—as is the case for DDR5—the desired system BER is ultra-low. Now, they need to accurately extrapolate the eye closure (the eye contour) down to 1e-16. Transient SPICE simulations ran out of steam for answering such questions, since it would take an impractical amount of time to simulate the digital logic-blocks (for equalizations) together with the analog channel for such large numbers of bits. By contrast, channel simulation with IBIS-AMI could arrive at the answer within minutes (to hours) depending on the number of bits to process.

Channel simulations are this fast because they use the process of linear superposition, meaning that if the analog part of the IBIS model, together with the passive channel can be characterized as LTI (linear and time-invariant), then we can process just 1 bit through the channel, and know that this response can be overlaid and summed to other bits to create the full waveform. Assumptions must be made about the device, such as concerning ourselves only with the device in a static terminated state, not switching from one termination to another. The different states (swapping Tx and Rx models, or changing termination loads), would be handled as separate simulations.

Why Has This Method Not Been Used for Ddr Before?

A special adaption of channel simulation for DDR (using statistical channel simulation methods, not IBIS-AMI) has been used very successfully for DDR4/LPDDR4 simulations since 2014. Especially for answering the question: How much margin do I have (in all four corners) to the receiver BER mask (at 1e-16). This technique let the simulator apply some basic EQ, like optimized DFE taps, but crucially it did not give the user the ability to simulate realistic EQ models from silicon vendors.

With IBIS-AMI however, there is an existing ecosystem in place for the SI engineer to simulate with models from the memory controller vendor, together with models from the DRAM/data buffer/register vendor, to enable a total system simulation.

The Trouble with Standard IBIS-AMI, and the Resolution—DDR Enhanced AMI

There are several challenges in the use of AMI for DDR signals. The standard IBIS-AMI reference flow was designed for differential signaling. That means there are several assumptions that were made in the IBIS-AMI specification that do not fit well for DDR. Do not worry, each is able to be overcome with technology innovations, but first let’s detail what needs to change.

1. One Tx, One Rx

The Issue: The standard IBIS-AMI reference flow today considers one Tx and one Rx, with all neighboring transmitters and receivers, being treated as crosstalk sources.

The Impact: In DDR, there are tens of signals we need to simulate simultaneously. When verifying the performance of a memory channel, all signals are important, yet we do not want to have to run multiple sequential simulations in order to collect all the eye diagrams we need.

The Resolution: The EDA simulator can adapt to handle multiple Tx and Rx models in one simulation.

2. Single-ended DDR IO buffers have a different impedance when driving a 1 than when they drive a 0 (see Figure 1).

Figure. 1 Special characteristics of single-ended DDR signals.

The Issue: This means that the IBIS model will produce a different rise-time and a different fall-time. The eye is asymmetric. Standard IBIS-AMI today with the reference flow use a single step edge to calculate the channel response. The analog part of the IBIS model is characterized in this process. However, only the rising edge is used.

The Impact: There is a significant difference in eye shape, the eye contour shape, and the crossing points (the widest part of the eye). A secondary effect is that the optimal slicer voltage threshold (Vref) is typically higher for the case of the asymmetric eye.

The Resolution: The EDA simulator can characterize the channel with a rising step edge, and then again with a falling step edge. In a bit-by-bit mode of operation, the EDA tool will apply the individual responses to the leading or trailing edge of a bit appropriately. The final waveform as constructed by the EDA tool will be input to the AMI model using the GetWave function. The channel characterization and waveform construction are clearly departures from the standard reference flow; however, this has always traditionally been an area open to EDA vendors’ technology innovation (see Figure 2).

Figure. 2 Enhancing the standard IBIS-AMI reference flow to address the needs of DDR memory.

3. Single-ended signals have a DC component.

The Issue: Standard IBIS-AMI carries no common-mode, no DC information into the AMI processing.

The Impact: From one data line to the next, a small difference in DC offset may be amplified by the variable gain block. The simulator will determine where to place the Vref, but this calculation will be greatly affected if the DC information is not present and correctly processed by the receiver.

The Resolution: The DC offset as calculated by the EDA tool can be passed into the AMI model as a special parameter. This is already progressing through the IBIS-ATM task group.

4. The EQ has an external clock (the data strobe).

The Issue: In high-speed serial AMI models, the clock is recovered from the data stream, but in the case of DDR, the clock is provided externally. This has some interesting ramifications. First, is the case of jitter. If jitter is correlated on both the data and the data strobe (the clock for the data) then it will cancel out, as long as the two signals keep the same phase relationships. In DRAM though, this is not a given, and the clock can be skewed multiple unit intervals from the data (see Figure 3).

Figure. 3 The Strobed Eye – The jitter relationship between data and strobe and its impact on the data eye.

The Impact: Very significant differences in peak-to-peak jitter numbers, and amplitude noise which will reduce the accuracy of eye closure predictions down to low BERs, if this jitter mechanism is not taken into account.

The Resolution: The simulator can pass both waveforms, the data and the strobe, into the receiver AMI model by using a second GetWave function, so that the model can process the two waveforms together using the strobe to clock the data slicer.

Areas for Future Innovation

One area that raises questions from experienced memory designers, is how simultaneous switching noise (SSN) would be handled when it comes to using IBIS-AMI for DDR signals. SSN is generated when there are multiple ICs all switching at the same time (on/off/on/off), generating large peak current demands on the power plane. The power and ground planes have difficulty with such transient currents, consequently showing up as voltage noise on the power plane, and ground bounce on the ground plane. This, in turn, affects the performance of the IC, whose supply may droop at a crucial moment, change the IOs performance, and provide less voltage swing for the data, reducing the eye opening.

How can these time-varying effects be handled in simulation? For DDR3 and DDR4, these effects could be handled with power-aware IBIS 5.0 models and a transient SPICE simulator. But now, with IBIS-AMI, where the channel is treated as LTI can we deal with power awareness?

Designers have a priority order of what they need to address. First, they typically design for best SI, in parallel they design for best PI, and finally they verify how much the latter affects the former. IBIS-AMI is very much needed to ensure the optimal design of the PCB, DIMM, and package, and ensure that we have an open eye after 1e16 bits or more. For PI, we can analyze the PDN separately and make sure that we have designed for an optimal flat impedance to minimize ripple. And finally, if so desired, we can quantify the jitter profile and amplitude noise contribution that SSN gives us, using traditional means (transient sim) with the (*.ibs) analog portion of the IBIS-AMI model, and add this as an impairment to the DDR-enhanced AMI simulation. This technique has been compared to transient results,1 and to real measurements.2


As early adopters begin their first product designs that will use DDR5 and LPDDR5 chips, they will need to ensure that they have the correct simulation toolsets in place to consume the new IBIS-AMI models coming from silicon vendors. Some things remain constant: margins are diminishing, and simulation complexity is increasing; however, some EDA tools have speedily advanced to be ahead of the need.

The question may come to mind how to compare EDA tools at this time, and, for that I hope, the list of important issues here helps serve as a checklist to press upon your favorite vendors, both EDA and silicon PHY, and encourage a convergence towards a standardized reference flow for DDR.


1. T. Mido, “Study on Potential Feature Additions for Bit-by-Bit Simulation Technique to Address DDR5 Requirements,” Synopsys Japan, https://ibis.org/summits/feb19/mido.pdf.

2. H. Lee and C Cui, “Accurate Statistical-Based DDR4 Margin Estimation Using SSN Induced Jitter Model,” Keysight Technologies, https://literature.cdn.keysight.com/litweb/pdf/5992-2133EN.pdf.

Article was published in the SIJ January 2020 Print Issue, Technical Feature: Page 36.