Items Tagged with 'PAM4'

The PCIe standard has successfully doubled its per-lane bandwidth across seven generations while maintaining full backward compatibility. PCIe Gen8 continues this legacy, targeting 256 GT/s per lane using PAM4 signaling. However, with each new generation, achieving backward compatibility within the same mechanical envelope becomes increasingly complex. Follow along as Abhijit Wander explores how sustaining bandwidth scalability beyond Gen7 may ultimately require both electrical and mechanical innovation rather than purely material or footprint optimization.

Samtec expands its Eye Speed cable family with twinax cable specifically developed for 224 Gbps PAM4 systems.

Intra-pair skew is a crucial metric when working with multiple lines. Its behavior, measurements, and interpretations are closely linked to other forms of signal degradation, making the definition of a single skew value a nuanced issue that requires careful consideration. In this article, Gustavo Blando and Prashant Pappu introduce three distinct methods for measuring skew, providing options for a wide variety of contexts and skew measurement goals.

Channel operating margin (COM) is a well-documented IEEE standard that has been used successfully since 2014 in the design of channels and specification of interconnect. In this article, Rich Mellitz reflects on the COM origin story and considers the future of the standard.

As insatiable data needs continue to grow due to artificial intelligence demands, the adoption of PAM4 standard has paved the way for future PAM-level encoding schemes to address future bandwidth limitations, prolonging the life of copper interconnects.

Samtec has announced availability of its NovaRay cable assemblies that combine extreme density and performance by using 40% less space than traditional arrays to support 112 Gbps PAM4 per channel.

Semiconductor signal conditioning and signal recovery innovations have extended data rates by managing allowable signal-to-noise ratio (SNR) at progressively higher Nyquist frequencies. We have experienced how each successive signaling technology increases the electro-mechanical design resolution needed to address the channel physics while respecting the SNR of the chips. These movements throughout the years have provided a baseline of traditional design goals that lead us to better understand today’s 224 Gbps-PAM4 physical layer requirements.

In preparation for 224 Gb/s and beyond, Samtec engaged in a research project to characterize the transmission performance of emerging PCB material sets. Brandon Gore explores the current state of the art for PCBs and cables, comparing them and assessing the technology gap to fully support the insertion loss performance required for higher data rates.

Portfolio of products designed to support tech leaders, hyperscale data center, and enterprise customers to meet increasing demands of generative AI, ML, 1.6T networking, and other high-speed applications.

New software tools support faster 64 GT/s data transfer speeds using PAM4 multi-level signaling.