Items Tagged with 'PAM4'

ARTICLES

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Design for AMI: A New Integrated Workflow for Modeling 56G PAM4 SerDes Systems

In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.


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Convergence: Key to 224 Gbps PAM4 System Design

Convergence in technology is not a new idea. The concept infers that disparate technologies evolve to a closer association or integration over time. Convergence occurs when any number of technologies, such as micro twinax cables, ASIC design, interconnects, advanced IC packaging, and others combine to offer a unique system-level solution. Many see convergence as required for 224 Gbps PAM4 system performance. 


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PAM4: For Better and Worse

Is PAM4 worth the hassle?

That’s the question that will trigger your amygdala’s fight or flight response as you encounter the many annoyances that PAM4 brings to your world. Since you’re in a lab rather than a jungle, that fight or flight response might translate into sarcastic cracks like: “Right, that higher BER requirement makes it all so much easier—not.” “Good old NRZ, those were some fine bits. Remind me why I asked for this?” And, “dear NRZ, I never knew how much I loved you until I lost you.”


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