Items Tagged with 'Signal Integrity'

In this article, Bert Simonovich explores how to avoid “garbage in, garbage out” with field solvers by building an understanding of the nuances of PCB fabrication processes, the interpretation manufacturers’ data sheets, and the tool’s user interface.

In this article, Donald Telian supplies a reference point for making the task of implementing via impedances, thus removing via impedance discontinuities, less daunting. Read on to find out how he can help.

Past and present officers gather to celebrate IBIS – and cut the cake!

In this paper, John Baprawski gives an overview of modeling SerDes systems in a channel simulator, introduces the zero-cost tools available at SerDesDesign.com, and gives an example of simulating a SerDes system with Tx and Rx IBIS-AMI models – all to bring the SI engineer a low cost path for modeling and simulating SerDes systems.

Since the inception of IBIS, the IBIS Committee has been working to improve and accommodate limitations of the model. This article gives a synopsis of that history, along with detailing the latest version, IBIS 7.1.  

In this article, Donald Telian shares an excerpt from his new book, “Signal Integrity, In Practice,” exploring how optimizing SES both fixes problems and improves system performance. He posits it’s crucial for hardware and SI engineers to understand how to optimize SES; read on to see why he attributes such importance to it. 

If you’ve just started on the path of designing high-speed serial links or have designed dozens of your own, Don Telian’s Signal Integrity in Practice is the book that will accelerate your engineering judgment and possibly save you from multiple design spins. Eric Bogatin takes a closer look at what he considers a must-have book for new and experienced engineers.

In earlier DDR systems, the clock, command, and address signals (here in referred to as C/A) were distributed to multiple DRAMs using a forked topology, in which these signals propagate to all the DRAMs in the system at approximately the same time. The propagation delays on the command and address lines (in such systems) introduced timing skew into the system, limiting the operating frequency of the bus and eventually impacting the performance of these memory systems.