If you routinely give attention to trace impedance but are not accustomed to thinking about via impedance, this article is for you. Or, if you are paying attention to via impedance yet are unsure what dimensions will yield the right impedance, this will help with that too. So, when should I use an 8 mil drill?
Why Should I Care?
Although they are small, vias can significantly impact performance. This first became apparent when ¼ wavelength stubs crept into systems. A via stub left in a ¼ in. thick backplane can completely remove a 12 Gbps signal, per the approximation 3/12 (yes, just use 3 divided by Gbps and get inches).3 While stubs can be disastrous, via impedance mismatch is also increasingly problematic as data rates increase. But how can we better understand the impedance of vias?
Enter Via Modeling
Building Impedance Intuition
Figure 1 shows stripline trace impedance versus width, spacing, and distance to ground planes (X-axis represents W=S=H1=H2 per the cross-section view). Interestingly, all dimensions yield impedances close to what we typically want, and minor adjustments are used to dial in the value more precisely. For example, increasing either or both H values moves the reference plane further away, making the trace more inductive, thus raising the impedance (Z=sqrt[L/C]). Widening the trace (W) makes the trace more capacitive, thus lowering its impedance. Visualize how these two changes impact impedance, because we are about to apply them to via structures.
Figure 2 plots differential via impedance versus common drill sizes on the X-axis. Pad sizes are drill+10 mils and circular antipad sizes are drill+20 mils. Spacing is 1 mm as would be found under a BGA or near a connector. The first thing we notice is the range of impedances has increased more than 4× when compared to the range of trace impedances in Figure 1. This wider range makes via impedance more challenging to control. Like traces, we can make changes to a via’s structure to adjust its impedance. For example, widening the antipads—or connecting them into an oval “racetrack” shape—moves the reference plane further away (like increasing trace H in Figure 1) making the via barrel more inductive thus raising its impedance. In contrast, increasing the drill size widens the barrel (like increasing trace W) making it more capacitive, hence lowering its impedance.
Again, the challenge with vias is the 4×+ impedance range compared to the narrower range associated with traces—seen clearly by comparing Figure 1 and Figure 2. As structural adjustments for traces and vias have similar dimensions, they also have similar effects on impedance—perhaps 5 Ω or 10 Ω in either direction. As such it becomes difficult to get 16 or even 12 mil vias close to 100 Ω because their “natural” (i.e., no structural modifications) impedances are ~70 Ω. Thus, it should become apparent why 8 mil drills are gaining in popularity in a world somewhat reluctant to move towards 85Ω impedance—which is the “natural” impedance of the more common 10 mil via.
important consideration. So, when using the differential impedances shown in Figure 2, if your Dk is higher than 3.3, your impedance values will be lower. Likewise, if your Dk is lower than 3.3, your impedances will be higher. For example, as Dk ranges from 3.0 to 3.6, the Figure 2 impedances change ± ~4 Ω.
We should also discuss differential trace and via spacing. As traces or vias get closer together they become more capacitive and hence impedance decreases. While the trace impedances shown in Figure 1 can be increased ~10 Ω by separating the traces, via impedances will decrease from those shown in Figure 2 as vias move closer together. However, due to their associated pads, via barrels cannot move closer together than ~20 mils, making it difficult to decrease impedance by more than ~5 Ω.
Also, be advised that as we pass 28 Gbps NRZ data rate, we need to stop thinking of vias as a single impedance, but instead as a structure whose impedance dips at the pads and rises in the barrel. At this data rate those elements are within the relevant feature size and, therefore, are modeled separately.6
*This article is an excerpt from Donald Telian’s new book “Signal Integrity, In Practice.” A Practical Handbook for Hardware, SI, FPGA, and Layout Engineers. Available at Amazon.
Donald Telian is a Signal Integrity Consultant, the owner of SiGuys, and the author of the book “Signal Integrity, In Practice” now available at Amazon. He has worked in Signal Integrity for 40 years.